1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef __dml2_TOP_DCHUB_REGISTERS_H__ 6 #define __dml2_TOP_DCHUB_REGISTERS_H__ 7 8 #include "dml2_external_lib_deps.h" 9 // These types are uint32_t as they represent actual calculated register values for HW 10 11 struct dml2_display_dlg_regs { 12 uint32_t refcyc_h_blank_end; 13 uint32_t dlg_vblank_end; 14 uint32_t min_dst_y_next_start; 15 uint32_t refcyc_per_htotal; 16 uint32_t refcyc_x_after_scaler; 17 uint32_t dst_y_after_scaler; 18 uint32_t dst_y_prefetch; 19 uint32_t dst_y_per_vm_vblank; 20 uint32_t dst_y_per_row_vblank; 21 uint32_t dst_y_per_vm_flip; 22 uint32_t dst_y_per_row_flip; 23 uint32_t ref_freq_to_pix_freq; 24 uint32_t vratio_prefetch; 25 uint32_t vratio_prefetch_c; 26 uint32_t refcyc_per_tdlut_group; 27 uint32_t refcyc_per_pte_group_vblank_l; 28 uint32_t refcyc_per_pte_group_vblank_c; 29 uint32_t refcyc_per_pte_group_flip_l; 30 uint32_t refcyc_per_pte_group_flip_c; 31 uint32_t dst_y_per_pte_row_nom_l; 32 uint32_t dst_y_per_pte_row_nom_c; 33 uint32_t refcyc_per_pte_group_nom_l; 34 uint32_t refcyc_per_pte_group_nom_c; 35 uint32_t refcyc_per_line_delivery_pre_l; 36 uint32_t refcyc_per_line_delivery_pre_c; 37 uint32_t refcyc_per_line_delivery_l; 38 uint32_t refcyc_per_line_delivery_c; 39 uint32_t refcyc_per_vm_group_vblank; 40 uint32_t refcyc_per_vm_group_flip; 41 uint32_t refcyc_per_vm_req_vblank; 42 uint32_t refcyc_per_vm_req_flip; 43 uint32_t dst_y_offset_cur0; 44 uint32_t chunk_hdl_adjust_cur0; 45 uint32_t vready_after_vcount0; 46 uint32_t dst_y_delta_drq_limit; 47 uint32_t refcyc_per_vm_dmdata; 48 uint32_t dmdata_dl_delta; 49 uint32_t dst_y_svp_drq_limit; 50 51 // MRQ 52 uint32_t refcyc_per_meta_chunk_vblank_l; 53 uint32_t refcyc_per_meta_chunk_vblank_c; 54 uint32_t refcyc_per_meta_chunk_flip_l; 55 uint32_t refcyc_per_meta_chunk_flip_c; 56 uint32_t dst_y_per_meta_row_nom_l; 57 uint32_t dst_y_per_meta_row_nom_c; 58 uint32_t refcyc_per_meta_chunk_nom_l; 59 uint32_t refcyc_per_meta_chunk_nom_c; 60 }; 61 62 struct dml2_display_ttu_regs { 63 uint32_t qos_level_low_wm; 64 uint32_t qos_level_high_wm; 65 uint32_t min_ttu_vblank; 66 uint32_t qos_level_flip; 67 uint32_t refcyc_per_req_delivery_l; 68 uint32_t refcyc_per_req_delivery_c; 69 uint32_t refcyc_per_req_delivery_cur0; 70 uint32_t refcyc_per_req_delivery_pre_l; 71 uint32_t refcyc_per_req_delivery_pre_c; 72 uint32_t refcyc_per_req_delivery_pre_cur0; 73 uint32_t qos_level_fixed_l; 74 uint32_t qos_level_fixed_c; 75 uint32_t qos_level_fixed_cur0; 76 uint32_t qos_ramp_disable_l; 77 uint32_t qos_ramp_disable_c; 78 uint32_t qos_ramp_disable_cur0; 79 }; 80 81 struct dml2_display_arb_regs { 82 uint32_t max_req_outstanding; 83 uint32_t min_req_outstanding; 84 uint32_t sat_level_us; 85 uint32_t hvm_max_qos_commit_threshold; 86 uint32_t hvm_min_req_outstand_commit_threshold; 87 uint32_t compbuf_reserved_space_kbytes; 88 uint32_t compbuf_size; 89 uint32_t sdpif_request_rate_limit; 90 uint32_t allow_sdpif_rate_limit_when_cstate_req; 91 uint32_t dcfclk_deep_sleep_hysteresis; 92 uint32_t pstate_stall_threshold; 93 }; 94 95 struct dml2_cursor_dlg_regs{ 96 uint32_t dst_x_offset; // CURSOR0_DST_X_OFFSET 97 uint32_t dst_y_offset; // CURSOR0_DST_Y_OFFSET 98 uint32_t chunk_hdl_adjust; // CURSOR0_CHUNK_HDL_ADJUST 99 100 uint32_t qos_level_fixed; 101 uint32_t qos_ramp_disable; 102 }; 103 104 struct dml2_display_plane_rq_regs { 105 uint32_t chunk_size; 106 uint32_t min_chunk_size; 107 uint32_t dpte_group_size; 108 uint32_t mpte_group_size; 109 uint32_t swath_height; 110 uint32_t pte_row_height_linear; 111 112 // MRQ 113 uint32_t meta_chunk_size; 114 uint32_t min_meta_chunk_size; 115 }; 116 117 struct dml2_display_rq_regs { 118 struct dml2_display_plane_rq_regs rq_regs_l; 119 struct dml2_display_plane_rq_regs rq_regs_c; 120 uint32_t drq_expansion_mode; 121 uint32_t prq_expansion_mode; 122 uint32_t crq_expansion_mode; 123 uint32_t plane1_base_address; 124 uint32_t unbounded_request_enabled; 125 126 // MRQ 127 uint32_t mrq_expansion_mode; 128 }; 129 130 struct dml2_display_mcache_regs { 131 uint32_t mcache_id_first; 132 uint32_t mcache_id_second; 133 uint32_t split_location; 134 }; 135 136 struct dml2_hubp_pipe_mcache_regs { 137 struct { 138 struct dml2_display_mcache_regs p0; 139 struct dml2_display_mcache_regs p1; 140 } main; 141 struct { 142 struct dml2_display_mcache_regs p0; 143 struct dml2_display_mcache_regs p1; 144 } mall; 145 }; 146 147 struct dml2_dchub_per_pipe_register_set { 148 struct dml2_display_rq_regs rq_regs; 149 struct dml2_display_ttu_regs ttu_regs; 150 struct dml2_display_dlg_regs dlg_regs; 151 152 uint32_t det_size; 153 }; 154 155 struct dml2_dchub_watermark_regs { 156 /* watermarks */ 157 uint32_t urgent; 158 uint32_t sr_enter; 159 uint32_t sr_exit; 160 uint32_t sr_enter_z8; 161 uint32_t sr_exit_z8; 162 uint32_t uclk_pstate; 163 uint32_t fclk_pstate; 164 uint32_t temp_read_or_ppt; 165 uint32_t usr; 166 /* qos */ 167 uint32_t refcyc_per_trip_to_mem; 168 uint32_t refcyc_per_meta_trip_to_mem; 169 uint32_t frac_urg_bw_flip; 170 uint32_t frac_urg_bw_nom; 171 uint32_t frac_urg_bw_mall; 172 }; 173 174 enum dml2_dchub_watermark_reg_set_index { 175 DML2_DCHUB_WATERMARK_SET_A = 0, 176 DML2_DCHUB_WATERMARK_SET_B = 1, 177 DML2_DCHUB_WATERMARK_SET_C = 2, 178 DML2_DCHUB_WATERMARK_SET_D = 3, 179 DML2_DCHUB_WATERMARK_SET_NUM = 4, 180 }; 181 182 struct dml2_dchub_global_register_set { 183 struct dml2_display_arb_regs arb_regs; 184 struct dml2_dchub_watermark_regs wm_regs[DML2_DCHUB_WATERMARK_SET_NUM]; 185 unsigned int num_watermark_sets; 186 }; 187 188 #endif 189