Home
last modified time | relevance | path

Searched defs:x (Results 1 – 25 of 1491) sorted by relevance

12345678910>>...60

/drivers/phy/microchip/
A Dsparx5_serdes_regs.h73 #define SD10G_LANE_LANE_02_CFG_EN_ADV_SET(x)\ argument
1040 #define SD10G_LANE_LANE_DF_LOL_SET(x)\ argument
1042 #define SD10G_LANE_LANE_DF_LOL_GET(x)\ argument
2300 #define SD6G_LANE_LANE_DF_LOL_SET(x)\ argument
2302 #define SD6G_LANE_LANE_DF_LOL_GET(x)\ argument
2590 #define SD_CMU_CMU_45_RESERVED_SET(x)\ argument
2592 #define SD_CMU_CMU_45_RESERVED_GET(x)\ argument
2777 #define SD_LANE_MISC_RX_ENA_SET(x)\ argument
2779 #define SD_LANE_MISC_RX_ENA_GET(x)\ argument
2783 #define SD_LANE_MISC_MUX_ENA_SET(x)\ argument
[all …]
A Dlan966x_serdes_regs.h21 #define HSIO_SD_CFG_PHY_RESET_SET(x)\ argument
23 #define HSIO_SD_CFG_PHY_RESET_GET(x)\ argument
27 #define HSIO_SD_CFG_TX_RESET_SET(x)\ argument
29 #define HSIO_SD_CFG_TX_RESET_GET(x)\ argument
33 #define HSIO_SD_CFG_TX_RATE_SET(x)\ argument
35 #define HSIO_SD_CFG_TX_RATE_GET(x)\ argument
39 #define HSIO_SD_CFG_TX_INVERT_SET(x)\ argument
45 #define HSIO_SD_CFG_TX_EN_SET(x)\ argument
47 #define HSIO_SD_CFG_TX_EN_GET(x)\ argument
57 #define HSIO_SD_CFG_TX_CM_EN_SET(x)\ argument
[all …]
/drivers/gpu/drm/radeon/
A Drs600d.h33 #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18) argument
34 #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1) argument
656 #define NORMAL_POWER_SCLK_HILEN(x) ((x) << 0) argument
657 #define NORMAL_POWER_SCLK_LOLEN(x) ((x) << 4) argument
658 #define REDUCED_POWER_SCLK_HILEN(x) ((x) << 8) argument
659 #define REDUCED_POWER_SCLK_LOLEN(x) ((x) << 12) argument
660 #define POWER_D1_SCLK_HILEN(x) ((x) << 16) argument
661 #define POWER_D1_SCLK_LOLEN(x) ((x) << 20) argument
662 #define STATIC_SCREEN_HILEN(x) ((x) << 24) argument
663 #define STATIC_SCREEN_LOLEN(x) ((x) << 28) argument
[all …]
A Dr100d.h69 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument
70 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument
72 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument
73 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument
75 #define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2) argument
76 #define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1) argument
78 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument
79 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument
81 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument
848 #define REDUCED_SPEED_SCLK_SEL(x) ((x) << 17) argument
[all …]
A Drs690d.h34 #define G_00005F_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF) argument
36 #define S_000078_MC_IND_ADDR(x) (((x) & 0x1FF) << 0) argument
37 #define G_000078_MC_IND_ADDR(x) (((x) >> 0) & 0x1FF) argument
39 #define S_000078_MC_IND_WR_EN(x) (((x) & 0x1) << 9) argument
40 #define G_000078_MC_IND_WR_EN(x) (((x) >> 9) & 0x1) argument
55 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
56 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
58 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
59 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
61 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument
[all …]
A Dr420d.h32 #define S_0001F8_MC_IND_ADDR(x) (((x) & 0x7F) << 0) argument
33 #define G_0001F8_MC_IND_ADDR(x) (((x) >> 0) & 0x7F) argument
35 #define S_0001F8_MC_IND_WR_EN(x) (((x) & 0x1) << 8) argument
36 #define G_0001F8_MC_IND_WR_EN(x) (((x) >> 8) & 0x1) argument
43 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
44 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
46 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
47 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
49 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument
50 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument
[all …]
A Dr300d.h84 #define S_00015C_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) argument
85 #define G_00015C_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) argument
92 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
93 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
95 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
96 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
98 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument
99 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument
101 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) argument
102 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) argument
[all …]
A Dr520d.h41 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
42 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
44 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
45 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
47 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument
48 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument
50 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) argument
51 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) argument
53 #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) argument
54 #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) argument
[all …]
A Drs400d.h33 #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) argument
47 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
48 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
50 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
51 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
53 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument
54 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument
56 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) argument
57 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) argument
59 #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) argument
[all …]
A Drv515d.h210 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument
211 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument
213 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument
214 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument
216 #define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2) argument
217 #define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1) argument
219 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument
220 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument
222 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument
223 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) argument
[all …]
A Drv250d.h32 #define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0) argument
33 #define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7) argument
35 #define S_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 3) argument
36 #define G_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) >> 3) & 0x1) argument
38 #define S_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 4) argument
39 #define G_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) >> 4) & 0x1) argument
41 #define S_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 5) argument
42 #define G_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) >> 5) & 0x1) argument
44 #define S_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 6) argument
45 #define G_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) >> 6) & 0x1) argument
[all …]
A Dr600d.h111 # define CB_FORMAT(x) ((x) << 2) argument
382 #define S0_X(x) ((x) << 0) argument
383 #define S0_Y(x) ((x) << 4) argument
384 #define S1_X(x) ((x) << 8) argument
385 #define S1_Y(x) ((x) << 12) argument
386 #define S2_X(x) ((x) << 16) argument
387 #define S2_Y(x) ((x) << 20) argument
388 #define S3_X(x) ((x) << 24) argument
390 #define S4_X(x) ((x) << 0) argument
391 #define S4_Y(x) ((x) << 4) argument
[all …]
/drivers/net/ethernet/microchip/sparx5/
A Dsparx5_main_regs.h82 #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\ argument
4949 #define FDMA_CTRL_NRESET_SET(x)\ argument
4951 #define FDMA_CTRL_NRESET_GET(x)\ argument
4978 #define GCB_CHIP_ID_ONE_SET(x)\ argument
4980 #define GCB_CHIP_ID_ONE_GET(x)\ argument
7106 #define QS_INJ_CTRL_EOF_SET(x)\ argument
7108 #define QS_INJ_CTRL_EOF_GET(x)\ argument
7112 #define QS_INJ_CTRL_SOF_SET(x)\ argument
7114 #define QS_INJ_CTRL_SOF_GET(x)\ argument
7183 #define QSYS_ATOP_ATOP_SET(x)\ argument
[all …]
/drivers/media/platform/verisilicon/
A Drockchip_vpu2_regs.h14 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16) argument
15 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0) argument
17 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16) argument
18 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0) argument
21 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0) argument
129 #define VEPU_REG_CHECKPOINT_RESULT(x) \ argument
198 #define VEPU_REG_IDR_PIC_ID(x) (((x) & 0xf) << 1) argument
257 #define VEPU_REG_MB_WIDTH(x) (((x) & 0x1ff) << 8) argument
280 #define VEPU_REG_PPS_ID(x) (((x) & 0xff) << 24) argument
320 #define VDPU_REG_CONFIG_TILED_MODE_MSB(x) BIT(0) argument
[all …]
A Dhantro_g1_regs.h28 #define G1_REG_CONFIG_DEC_AXI_RD_ID(x) (((x) & 0xff) << 24) argument
37 #define G1_REG_CONFIG_DEC_LATENCY(x) (((x) & 0x3f) << 11) argument
41 #define G1_REG_CONFIG_PRIORITY_MODE(x) (((x) & 0x7) << 5) argument
45 #define G1_REG_CONFIG_DEC_MAX_BURST(x) (((x) & 0x1f) << 0) argument
47 #define G1_REG_DEC_CTRL0_DEC_MODE(x) (((x) & 0xf) << 28) argument
101 #define G1_REG_DEC_CTRL2_MVTAB(x) (((x) & 0x7) << 7) argument
102 #define G1_REG_DEC_CTRL2_CBPTAB(x) (((x) & 0x7) << 4) argument
111 #define G1_REG_DEC_CTRL2_JPEG_MODE(x) (((x) & 0x7) << 8) argument
146 #define G1_REG_DEC_CTRL4_DQ_EDGES(x) (((x) & 0xf) << 20) argument
153 #define G1_REG_DEC_CTRL4_TTFRM(x) (((x) & 0x3) << 8) argument
[all …]
/drivers/net/ethernet/microchip/lan966x/
A Dlan966x_regs.h74 #define ANA_ANAINTR_INTR_SET(x)\ argument
76 #define ANA_ANAINTR_INTR_GET(x)\ argument
80 #define ANA_ANAINTR_INTR_ENA_SET(x)\ argument
164 #define ANA_PGID_PGID_SET(x)\ argument
166 #define ANA_PGID_PGID_GET(x)\ argument
1067 #define PTP_DOM_CFG_ENA_SET(x)\ argument
1069 #define PTP_DOM_CFG_ENA_GET(x)\ argument
1239 #define QS_INJ_CTRL_EOF_SET(x)\ argument
1241 #define QS_INJ_CTRL_EOF_GET(x)\ argument
1245 #define QS_INJ_CTRL_SOF_SET(x)\ argument
[all …]
/drivers/net/ethernet/chelsio/cxgb/
A Dregs.h197 #define V_DAY(x) ((x) << S_DAY) argument
202 #define V_MONTH(x) ((x) << S_MONTH) argument
252 #define V_READY(x) ((x) << S_READY) argument
304 #define V_BANKS(x) ((x) << S_BANKS) argument
328 #define V_BUSY(x) ((x) << S_BUSY) argument
459 #define V_OP(x) ((x) << S_OP) argument
845 #define V_SACK(x) ((x) << S_SACK) argument
850 #define V_ECN(x) ((x) << S_ECN) argument
859 #define V_MSS(x) ((x) << S_MSS) argument
1043 #define V_2MSL(x) ((x) << S_2MSL) argument
[all …]
/drivers/gpu/drm/amd/amdgpu/
A Dsoc15d.h80 #define CP_PACKETJ_GET_REG(x) ((x) & 0x3FFFF) argument
81 #define CP_PACKETJ_GET_RES(x) (((x) >> 18) & 0x3F) argument
82 #define CP_PACKETJ_GET_COND(x) (((x) >> 24) & 0xF) argument
83 #define CP_PACKETJ_GET_TYPE(x) (((x) >> 28) & 0xF) argument
88 #define PACKET3_BASE_INDEX(x) ((x) << 0) argument
130 #define WRITE_DATA_DST_SEL(x) ((x) << 8) argument
178 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) argument
211 #define PACKET3_WAIT_REG_MEM__MASK(x) ((unsigned)(x)) argument
233 #define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) argument
258 #define PACKET3_COPY_DATA__IMM_DATA(x) ((unsigned)(x)) argument
[all …]
A Dnvd.h57 #define PACKET3_BASE_INDEX(x) ((x) << 0) argument
70 #define PACKET3_ATOMIC_MEM__ADDR_LO(x) (((unsigned)(x))) argument
71 #define PACKET3_ATOMIC_MEM__ADDR_HI(x) (((unsigned)(x))) argument
201 #define PACKET3_WAIT_REG_MEM__MASK(x) ((unsigned)(x)) argument
231 #define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) argument
355 #define PACKET3_RELEASE_MEM_EVENT_TYPE(x) ((x) << 0) argument
356 #define PACKET3_RELEASE_MEM_EVENT_INDEX(x) ((x) << 8) argument
375 #define PACKET3_RELEASE_MEM_DATA_SEL(x) ((x) << 29) argument
382 #define PACKET3_RELEASE_MEM_INT_SEL(x) ((x) << 24) argument
387 #define PACKET3_RELEASE_MEM_DST_SEL(x) ((x) << 16) argument
[all …]
A Dnavi10_sdma_pkt_open.h78 #define SDMA_GCR_SEQ(x) (((x) & 0x3) << 16) argument
82 #define SDMA_GCR_GL2_RANGE(x) (((x) & 0x3) << 11) argument
90 #define SDMA_GCR_GL1_RANGE(x) (((x) & 0x3) << 2) argument
91 #define SDMA_GCR_GLI_INV(x) (((x) & 0x3) << 0) argument
97 #define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift) argument
103 #define SDMA_PKT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_sh… argument
3464 #define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER… argument
3527 #define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_d… argument
4291 #define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op… argument
4504 #define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_sh… argument
[all …]
A Diceland_sdma_pkt_open.h57 #define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift) argument
63 #define SDMA_PKT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_sh… argument
538 #define SDMA_PKT_COPY_TILED_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TIL… argument
544 #define SDMA_PKT_COPY_TILED_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TIL… argument
551 #define SDMA_PKT_COPY_TILED_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TIL… argument
1748 #define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER… argument
1775 #define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_d… argument
1825 #define SDMA_PKT_PRE_EXE_HEADER_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_… argument
2133 #define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op… argument
2158 #define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_sh… argument
[all …]
A Dsdma_v6_0_0_pkt_open.h80 #define SDMA_GCR_SEQ(x) (((x) & 0x3) << 16) argument
84 #define SDMA_GCR_GL2_RANGE(x) (((x) & 0x3) << 11) argument
92 #define SDMA_GCR_GL1_RANGE(x) (((x) & 0x3) << 2) argument
93 #define SDMA_GCR_GLI_INV(x) (((x) & 0x3) << 0) argument
95 #define SDMA_DCC_DATA_FORMAT(x) ((x) & 0x3f) argument
96 #define SDMA_DCC_NUM_TYPE(x) (((x) & 0x7) << 9) argument
97 #define SDMA_DCC_READ_CM(x) (((x) & 0x3) << 16) argument
98 #define SDMA_DCC_WRITE_CM(x) (((x) & 0x3) << 18) argument
99 #define SDMA_DCC_MAX_COM(x) (((x) & 0x3) << 24) argument
100 #define SDMA_DCC_MAX_UCOM(x) (((x) & 0x1) << 26) argument
[all …]
/drivers/net/ethernet/chelsio/cxgb3/
A Dsge_defs.h11 #define V_EC_CREDITS(x) ((x) << S_EC_CREDITS) argument
15 #define V_EC_GTS(x) ((x) << S_EC_GTS) argument
20 #define V_EC_INDEX(x) ((x) << S_EC_INDEX) argument
25 #define V_EC_SIZE(x) ((x) << S_EC_SIZE) argument
45 #define V_EC_TYPE(x) ((x) << S_EC_TYPE) argument
49 #define V_EC_GEN(x) ((x) << S_EC_GEN) argument
71 #define V_RQ_GEN(x) ((x) << S_RQ_GEN) argument
107 #define V_CQ_GEN(x) ((x) << S_CQ_GEN) argument
111 #define V_CQ_ERR(x) ((x) << S_CQ_ERR) argument
149 #define V_FL_GEN(x) ((x) << S_FL_GEN) argument
[all …]
A Dregs.h5 #define V_CONGMODE(x) ((x) << S_CONGMODE) argument
17 #define V_DROPPKT(x) ((x) << S_DROPPKT) argument
33 #define V_FLMODE(x) ((x) << S_FLMODE) argument
82 #define V_RSPQ(x) ((x) << S_RSPQ) argument
113 #define V_CQ(x) ((x) << S_CQ) argument
804 #define V_OP(x) ((x) << S_OP) argument
822 #define V_AE(x) ((x) << S_AE) argument
828 #define V_PE(x) ((x) << S_PE) argument
833 #define V_UE(x) ((x) << S_UE) argument
837 #define V_CE(x) ((x) << S_CE) argument
[all …]
/drivers/net/ethernet/chelsio/cxgb4/
A Dt4_regs.h77 #define QID_V(x) ((x) << QID_S) argument
84 #define PIDX_V(x) ((x) << PIDX_S) argument
162 #define BUSY_V(x) ((x) << BUSY_S) argument
773 #define BIR_V(x) ((x) << BIR_S) argument
2873 #define OP_V(x) ((x) << OP_S) argument
2926 #define MA_V(x) ((x) << MA_S) argument
2930 #define TP_V(x) ((x) << TP_S) argument
2934 #define LE_V(x) ((x) << LE_S) argument
2946 #define MC_V(x) ((x) << MC_S) argument
2974 #define SF_V(x) ((x) << SF_S) argument
[all …]

Completed in 1030 milliseconds

12345678910>>...60