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/include/soc/mscc/
A Docelot_ana.h19 #define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0)) argument
28 #define ANA_STORMLIMIT_CFG_STORM_MODE(x) ((x) & GENMASK(1, 0)) argument
64 #define ANA_FLOODING_FLD_MULTICAST(x) ((x) & GENMASK(5, 0)) argument
76 #define ANA_FLOODING_IPMC_FLD_MC6_DATA(x) ((x) & GENMASK(5, 0)) argument
99 #define ANA_PGID_PGID_PGID(x) ((x) & GENMASK(11, 0)) argument
108 #define ANA_TABLES_MACHDATA_MACHDATA(x) ((x) & GENMASK(15, 0)) argument
116 #define ANA_TABLES_STREAMDATA_SFID(x) ((x) & GENMASK(7, 0)) argument
130 #define ANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) ((x) & GENMASK(2, 0)) argument
144 #define ANA_TABLES_VLANACCESS_VLAN_TBL_CMD(x) ((x) & GENMASK(1, 0)) argument
162 #define ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD(x) ((x) & GENMASK(1, 0)) argument
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A Docelot_qsys.h28 #define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x) ((x) & GENMASK(7, 0)) argument
36 #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK(x) ((x) & GENMASK(7, 0)) argument
47 #define QSYS_QMAP_SE_INP_SEL(x) ((x) & GENMASK(1, 0)) argument
59 #define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT(x) ((x) & GENMASK(6, 0)) argument
67 #define QSYS_RED_PROFILE_WM_RED_HIGH(x) ((x) & GENMASK(7, 0)) argument
74 #define QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(x) ((x) & GENMASK(15, 0)) argument
80 #define QSYS_EVENTS_CORE_EV_FRD(x) ((x) & GENMASK(1, 0)) argument
101 #define QSYS_PREEMPTION_CFG_P_QUEUES(x) ((x) & GENMASK(7, 0)) argument
118 #define QSYS_CIR_CFG_CIR_BURST(x) ((x) & GENMASK(5, 0)) argument
183 #define QSYS_CIR_STATE_SHP_TIME(x) ((x) & GENMASK(3, 0)) argument
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A Docelot_hsio.h106 #define HSIO_PLL5G_CFG0_CORE_CLK_DIV(x) ((x) & GENMASK(5, 0)) argument
166 #define HSIO_PLL5G_CFG3_FBDIVSEL(x) ((x) & GENMASK(7, 0)) argument
172 #define HSIO_PLL5G_CFG4_IB_CTRL(x) ((x) & GENMASK(15, 0)) argument
178 #define HSIO_PLL5G_CFG5_OB_CTRL(x) ((x) & GENMASK(15, 0)) argument
194 #define HSIO_PLL5G_CFG6_DDR_CLK_DIV(x) ((x) & GENMASK(5, 0)) argument
228 #define HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE(x) ((x) & GENMASK(15, 0)) argument
253 #define HSIO_RCOMP_CFG0_RCOMP_VAL(x) ((x) & GENMASK(3, 0)) argument
258 #define HSIO_RCOMP_STATUS_RCOMP(x) ((x) & GENMASK(3, 0)) argument
310 #define HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0)) argument
327 #define HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL(x) ((x) & GENMASK(3, 0)) argument
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A Docelot_sys.h20 #define SYS_FRM_AGING_MAX_AGE(x) ((x) & GENMASK(19, 0)) argument
26 #define SYS_STAT_CFG_STAT_VIEW(x) ((x) & GENMASK(9, 0)) argument
43 #define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET(x) ((x) & GENMASK(5, 0)) argument
49 #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP(x) ((x) & GENMASK(8, 0)) argument
65 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG(x) ((x) & GENMASK(15, 0)) argument
71 #define SYS_MMGT_FREECNT(x) ((x) & GENMASK(15, 0)) argument
77 #define SYS_MMGT_FAST_RELVLD(x) ((x) & GENMASK(3, 0)) argument
85 #define SYS_EVENTS_DIF_EV_DTX(x) ((x) & GENMASK(5, 0)) argument
89 #define SYS_EVENTS_CORE_EV_ANA(x) ((x) & GENMASK(1, 0)) argument
103 #define SYS_PTP_STATUS_PTP_MESS_SEQ_ID(x) ((x) & GENMASK(15, 0)) argument
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A Docelot_dev.h17 #define DEV_CLOCK_CFG_LINK_SPEED(x) ((x) & GENMASK(1, 0)) argument
27 #define DEV_EEE_CFG_EEE_TIMER_AGE(x) (((x) << 15) & GENMASK(21, 15)) argument
30 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x) (((x) << 8) & GENMASK(14, 8)) argument
32 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x) (((x) & GENMASK(14, 8)) >> 8) argument
33 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x) (((x) << 1) & GENMASK(7, 1)) argument
35 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_X(x) (((x) & GENMASK(7, 1)) >> 1) argument
38 #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG(x) (((x) << 4) & GENMASK(11, 4)) argument
40 #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_X(x) (((x) & GENMASK(11, 4)) >> 4) argument
41 #define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG(x) ((x) & GENMASK(3, 0)) argument
68 #define DEV_MAC_IFG_CFG_RX_IFG1(x) ((x) & GENMASK(3, 0)) argument
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/include/uapi/linux/byteorder/
A Dbig_endian.h16 #define __constant_htonl(x) ((__force __be32)(__u32)(x)) argument
17 #define __constant_ntohl(x) ((__force __u32)(__be32)(x)) argument
18 #define __constant_htons(x) ((__force __be16)(__u16)(x)) argument
19 #define __constant_ntohs(x) ((__force __u16)(__be16)(x)) argument
38 #define __cpu_to_be64(x) ((__force __be64)(__u64)(x)) argument
93 #define __cpu_to_le64s(x) __swab64s((x)) argument
94 #define __le64_to_cpus(x) __swab64s((x)) argument
95 #define __cpu_to_le32s(x) __swab32s((x)) argument
96 #define __le32_to_cpus(x) __swab32s((x)) argument
97 #define __cpu_to_le16s(x) __swab16s((x)) argument
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A Dlittle_endian.h32 #define __cpu_to_le64(x) ((__force __le64)(__u64)(x)) argument
33 #define __le64_to_cpu(x) ((__force __u64)(__le64)(x)) argument
34 #define __cpu_to_le32(x) ((__force __le32)(__u32)(x)) argument
35 #define __le32_to_cpu(x) ((__force __u32)(__le32)(x)) argument
36 #define __cpu_to_le16(x) ((__force __le16)(__u16)(x)) argument
99 #define __cpu_to_be64s(x) __swab64s((x)) argument
100 #define __be64_to_cpus(x) __swab64s((x)) argument
101 #define __cpu_to_be32s(x) __swab32s((x)) argument
102 #define __be32_to_cpus(x) __swab32s((x)) argument
103 #define __cpu_to_be16s(x) __swab16s((x)) argument
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/include/trace/misc/
A Drdma.h34 #define ib_event(x) TRACE_DEFINE_ENUM(IB_EVENT_##x); argument
42 #define ib_event(x) { IB_EVENT_##x, #x }, argument
43 #define ib_event_end(x) { IB_EVENT_##x, #x } argument
45 #define rdma_show_ib_event(x) \ argument
86 #define ib_wc_status(x) { IB_WC_##x, #x }, argument
87 #define ib_wc_status_end(x) { IB_WC_##x, #x } argument
89 #define rdma_show_wc_status(x) \ argument
126 #define ib_cm_event(x) { IB_CM_##x, #x }, argument
127 #define ib_cm_event_end(x) { IB_CM_##x, #x } argument
129 #define rdma_show_ib_cm_event(x) \ argument
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A Dnfs.h46 #define show_nfs_status(x) \ argument
86 #define show_nfs_stable_how(x) \ argument
200 #define show_nfs4_status(x) \ argument
350 #define show_nfs4_verifier(x) \ argument
357 #define show_pnfs_layout_iomode(x) \ argument
363 #define show_rca_mask(x) \ argument
375 #define show_nfs4_seq4_status(x) \ argument
404 #define show_nfs4_cb_op(x) \ argument
A Dfs.h12 #define show_fs_dirent_type(x) \ argument
24 #define show_fs_fcntl_open_flags(x) \ argument
42 #define __fmode_flag(x) { (__force unsigned long)FMODE_##x, #x } argument
43 #define show_fs_fmode_flags(x) \ argument
50 #define show_fs_fcntl_cmd(x) \ argument
71 #define show_fs_fcntl_cmd(x) \ argument
96 #define show_fs_fcntl_lock_type(x) \ argument
/include/asm-generic/
A Dint-ll64.h25 #define S8_C(x) x argument
27 #define S16_C(x) x argument
29 #define S32_C(x) x argument
36 #define S8_C(x) x argument
37 #define U8_C(x) x argument
38 #define S16_C(x) x argument
39 #define U16_C(x) x argument
40 #define S32_C(x) x argument
41 #define U32_C(x) x argument
42 #define S64_C(x) x argument
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/include/linux/
A Dbitrev.h21 static inline u16 __bitrev16(u16 x) in __bitrev16()
26 static inline u32 __bitrev32(u32 x) in __bitrev32()
33 #define __bitrev8x4(x) (__bitrev32(swab32(x))) argument
35 #define __constant_bitrev32(x) \ argument
46 #define __constant_bitrev16(x) \ argument
56 #define __constant_bitrev8x4(x) \ argument
65 #define __constant_bitrev8(x) \ argument
74 #define bitrev32(x) \ argument
82 #define bitrev16(x) \ argument
90 #define bitrev8x4(x) \ argument
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A Dmem_encrypt.h27 #define __sme_set(x) ((x) | sme_me_mask) argument
28 #define __sme_clr(x) ((x) & ~sme_me_mask) argument
30 #define dma_addr_encrypted(x) __sme_set(x) argument
31 #define dma_addr_canonical(x) __sme_clr(x) argument
34 #define __sme_set(x) (x) argument
35 #define __sme_clr(x) (x) argument
46 #define dma_addr_encrypted(x) (x) argument
50 #define dma_addr_unencrypted(x) (x) argument
54 #define dma_addr_canonical(x) (x) argument
A Dbcd.h7 #define bcd2bin(x) \ argument
12 #define bin2bcd(x) \ argument
17 #define bcd_is_valid(x) \ argument
20 #define const_bcd2bin(x) (((x) & 0x0f) + ((x) >> 4) * 10) argument
21 #define const_bin2bcd(x) ((((x) / 10) << 4) + (x) % 10) argument
22 #define const_bcd_is_valid(x) (((x) & 0x0f) < 10 && ((x) >> 4) < 10) argument
A Dmath.h15 #define __round_mask(x, y) ((__typeof__(x))((y)-1)) argument
25 #define round_up(x, y) ((((x)-1) | __round_mask(x, y))+1) argument
35 #define round_down(x, y) ((x) & ~__round_mask(x, y)) argument
71 #define roundup(x, y) ( \ argument
85 #define rounddown(x, y) ( \ argument
98 #define DIV_ROUND_CLOSEST(x, divisor)( \ argument
113 #define DIV_ROUND_CLOSEST_ULL(x, divisor)( \ argument
136 #define mult_frac(x, n, d) \ in __STRUCT_FRACT() argument
157 #define abs(x) __abs_choose_expr(x, long long, \ argument
167 #define __abs_choose_expr(x, type, other) __builtin_choose_expr( \ argument
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/include/media/
A Dv4l2-cci.h43 #define CCI_REG_WIDTH_BYTES(x) FIELD_GET(CCI_REG_WIDTH_MASK, x) argument
44 #define CCI_REG_WIDTH(x) (CCI_REG_WIDTH_BYTES(x) << 3) argument
45 #define CCI_REG_ADDR(x) FIELD_GET(CCI_REG_ADDR_MASK, x) argument
48 #define CCI_REG8(x) ((1 << CCI_REG_WIDTH_SHIFT) | (x)) argument
49 #define CCI_REG16(x) ((2 << CCI_REG_WIDTH_SHIFT) | (x)) argument
50 #define CCI_REG24(x) ((3 << CCI_REG_WIDTH_SHIFT) | (x)) argument
51 #define CCI_REG32(x) ((4 << CCI_REG_WIDTH_SHIFT) | (x)) argument
52 #define CCI_REG64(x) ((8 << CCI_REG_WIDTH_SHIFT) | (x)) argument
53 #define CCI_REG16_LE(x) (CCI_REG_LE | (2U << CCI_REG_WIDTH_SHIFT) | (x)) argument
54 #define CCI_REG24_LE(x) (CCI_REG_LE | (3U << CCI_REG_WIDTH_SHIFT) | (x)) argument
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/include/trace/events/
A Drdma_core.h31 #define ib_poll_ctx(x) TRACE_DEFINE_ENUM(IB_POLL_##x); argument
32 #define ib_poll_ctx_end(x) TRACE_DEFINE_ENUM(IB_POLL_##x); argument
39 #define ib_poll_ctx(x) { IB_POLL_##x, #x }, argument
40 #define ib_poll_ctx_end(x) { IB_POLL_##x, #x } argument
42 #define rdma_show_ib_poll_ctx(x) \ argument
287 #define ib_mr_type_item(x) TRACE_DEFINE_ENUM(IB_MR_TYPE_##x); argument
288 #define ib_mr_type_end(x) TRACE_DEFINE_ENUM(IB_MR_TYPE_##x); argument
295 #define ib_mr_type_item(x) { IB_MR_TYPE_##x, #x }, argument
296 #define ib_mr_type_end(x) { IB_MR_TYPE_##x, #x } argument
298 #define rdma_show_ib_mr_type(x) \ argument
A Dhandshake.h24 #define record_type(x) TRACE_DEFINE_ENUM(TLS_RECORD_TYPE_##x); argument
25 #define record_type_end(x) TRACE_DEFINE_ENUM(TLS_RECORD_TYPE_##x); argument
31 #define record_type(x) { TLS_RECORD_TYPE_##x, #x }, argument
32 #define record_type_end(x) { TLS_RECORD_TYPE_##x, #x } argument
77 #define alert_description(x) TRACE_DEFINE_ENUM(TLS_ALERT_DESC_##x); argument
78 #define alert_description_end(x) TRACE_DEFINE_ENUM(TLS_ALERT_DESC_##x); argument
84 #define alert_description(x) { TLS_ALERT_DESC_##x, #x }, argument
85 #define alert_description_end(x) { TLS_ALERT_DESC_##x, #x } argument
/include/uapi/linux/
A Dswab.h14 #define ___constant_swab16(x) ((__u16)( \ argument
18 #define ___constant_swab32(x) ((__u32)( \ argument
24 #define ___constant_swab64(x) ((__u64)( \ argument
34 #define ___constant_swahw32(x) ((__u32)( \ argument
38 #define ___constant_swahb32(x) ((__u32)( \ argument
102 #define __swab16(x) (__u16)__builtin_bswap16((__u16)(x)) argument
104 #define __swab16(x) \ argument
117 #define __swab32(x) \ argument
130 #define __swab64(x) \ argument
151 #define __swahw32(x) \ argument
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/include/linux/mtd/
A Dcfi_endian.h27 #define cpu_to_cfi8(map, x) (x) argument
28 #define cfi8_to_cpu(map, x) (x) argument
29 #define cpu_to_cfi16(map, x) _cpu_to_cfi(16, (map)->swap, (x)) argument
30 #define cpu_to_cfi32(map, x) _cpu_to_cfi(32, (map)->swap, (x)) argument
31 #define cpu_to_cfi64(map, x) _cpu_to_cfi(64, (map)->swap, (x)) argument
32 #define cfi16_to_cpu(map, x) _cfi_to_cpu(16, (map)->swap, (x)) argument
33 #define cfi32_to_cpu(map, x) _cfi_to_cpu(32, (map)->swap, (x)) argument
34 #define cfi64_to_cpu(map, x) _cfi_to_cpu(64, (map)->swap, (x)) argument
36 #define _cpu_to_cfi(w, s, x) (cfi_host(s)?(x):_swap_to_cfi(w, s, x)) argument
37 #define _cfi_to_cpu(w, s, x) (cfi_host(s)?(x):_swap_to_cpu(w, s, x)) argument
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/include/dt-bindings/sound/
A Dfsl-imx-audmux.h36 #define IMX_AUDMUX_V1_PCR_INMMASK(x) ((x) & 0xff) argument
40 #define IMX_AUDMUX_V1_PCR_RXDSEL(x) (((x) & 0x7) << 13) argument
41 #define IMX_AUDMUX_V1_PCR_RFCSEL(x) (((x) & 0xf) << 20) argument
44 #define IMX_AUDMUX_V1_PCR_TFCSEL(x) (((x) & 0xf) << 26) argument
50 #define IMX_AUDMUX_V2_PTCR_TFSEL(x) (((x) & 0xf) << 27) argument
52 #define IMX_AUDMUX_V2_PTCR_TCSEL(x) (((x) & 0xf) << 22) argument
54 #define IMX_AUDMUX_V2_PTCR_RFSEL(x) (((x) & 0xf) << 17) argument
56 #define IMX_AUDMUX_V2_PTCR_RCSEL(x) (((x) & 0xf) << 12) argument
59 #define IMX_AUDMUX_V2_PDCR_RXDSEL(x) (((x) & 0x7) << 13) argument
61 #define IMX_AUDMUX_V2_PDCR_MODE(x) (((x) & 0x3) << 8) argument
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/include/scsi/
A Dscsi_transport_spi.h62 #define spi_period(x) (((struct spi_transport_attrs *)&(x)->starget_data)->period) argument
64 #define spi_offset(x) (((struct spi_transport_attrs *)&(x)->starget_data)->offset) argument
66 #define spi_width(x) (((struct spi_transport_attrs *)&(x)->starget_data)->width) argument
68 #define spi_iu(x) (((struct spi_transport_attrs *)&(x)->starget_data)->iu) argument
69 #define spi_max_iu(x) (((struct spi_transport_attrs *)&(x)->starget_data)->max_iu) argument
70 #define spi_dt(x) (((struct spi_transport_attrs *)&(x)->starget_data)->dt) argument
71 #define spi_qas(x) (((struct spi_transport_attrs *)&(x)->starget_data)->qas) argument
72 #define spi_max_qas(x) (((struct spi_transport_attrs *)&(x)->starget_data)->max_qas) argument
73 #define spi_wr_flow(x) (((struct spi_transport_attrs *)&(x)->starget_data)->wr_flow) argument
75 #define spi_rti(x) (((struct spi_transport_attrs *)&(x)->starget_data)->rti) argument
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/include/linux/mfd/
A Dsun4i-gpadc.h12 #define SUN4I_GPADC_CTRL0_ADC_FIRST_DLY(x) ((GENMASK(7, 0) & (x)) << 24) argument
15 #define SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(x) ((GENMASK(1, 0) & (x)) << 20) argument
16 #define SUN4I_GPADC_CTRL0_FS_DIV(x) ((GENMASK(3, 0) & (x)) << 16) argument
17 #define SUN4I_GPADC_CTRL0_T_ACQ(x) (GENMASK(15, 0) & (x)) argument
21 #define SUN4I_GPADC_CTRL1_STYLUS_UP_DEBOUNCE(x) ((GENMASK(7, 0) & (x)) << 12) argument
27 #define SUN4I_GPADC_CTRL1_ADC_CHAN_SELECT(x) (GENMASK(2, 0) & (x)) argument
35 #define SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(x) (GENMASK(3, 0) & BIT(x)) argument
45 #define SUN4I_GPADC_CTRL2_TP_MODE_SELECT(x) ((GENMASK(1, 0) & (x)) << 26) argument
47 #define SUN4I_GPADC_CTRL2_PRE_MEA_THRE_CNT(x) (GENMASK(23, 0) & (x)) argument
52 #define SUN4I_GPADC_CTRL3_FILTER_TYPE(x) (GENMASK(1, 0) & (x)) argument
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/include/video/
A Dili9320.h12 #define ILI9320_REG(x) (x) argument
97 #define ILI9320_DISPLAY1_D(x) ((x) << 0) argument
129 #define ILI9320_POWER1_AP(x) ((x) << 4) argument
131 #define ILI9320_POWER1_BT(x) ((x) << 8) argument
135 #define ILI9320_POWER2_VC(x) ((x) << 0) argument
136 #define ILI9320_POWER2_DC0(x) ((x) << 4) argument
137 #define ILI9320_POWER2_DC1(x) ((x) << 8) argument
140 #define ILI9320_POWER3_VRH(x) ((x) << 0) argument
149 #define ILI9320_DRIVER2_NL(x) ((x) << 8) argument
158 #define ILI9320_INTERFACE4_RTNE(x) (x) argument
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/include/linux/iio/frequency/
A Dadf4350.h20 #define ADF4350_REG0_FRACT(x) (((x) & 0xFFF) << 3) argument
21 #define ADF4350_REG0_INT(x) (((x) & 0xFFFF) << 15) argument
24 #define ADF4350_REG1_MOD(x) (((x) & 0xFFF) << 3) argument
25 #define ADF4350_REG1_PHASE(x) (((x) & 0xFFF) << 15) argument
39 #define ADF4350_REG2_10BIT_R_CNT(x) ((x) << 14) argument
42 #define ADF4350_REG2_MUXOUT(x) ((x) << 26) argument
53 #define ADF4350_REG3_12BIT_CLKDIV(x) ((x) << 3) argument
54 #define ADF4350_REG3_12BIT_CLKDIV_MODE(x) ((x) << 16) argument
61 #define ADF4350_REG4_OUTPUT_PWR(x) ((x) << 3) argument
63 #define ADF4350_REG4_AUX_OUTPUT_PWR(x) ((x) << 6) argument
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