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Searched refs:val (Results 1 – 25 of 1206) sorted by relevance

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/arch/alpha/lib/
A Dfpreg.c15 #define STT(reg,val) asm volatile ("ftoit $f"#reg",%0" : "=r"(val)); argument
17 #define STT(reg,val) asm volatile ("stt $f"#reg",%0" : "=m"(val)); argument
23 unsigned long val; in alpha_read_fp_reg() local
65 return val; in alpha_read_fp_reg()
70 #define LDT(reg,val) asm volatile ("itoft %0,$f"#reg : : "r"(val)); argument
72 #define LDT(reg,val) asm volatile ("ldt $f"#reg",%0" : : "m"(val)); argument
124 #define STS(reg,val) asm volatile ("ftois $f"#reg",%0" : "=r"(val)); argument
126 #define STS(reg,val) asm volatile ("sts $f"#reg",%0" : "=m"(val)); argument
140 STS(0, val); in alpha_read_fp_reg_s()
176 return val; in alpha_read_fp_reg_s()
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/arch/arm/include/asm/hardware/
A Dcp14.h12 #define dbg_write(val, reg) WCP14_##reg(val) argument
14 #define etm_write(val, reg) WCP14_##reg(val) argument
21 val; \
153 #define WCP14_DBGWFAR(val) MCR14(val, 0, c0, c6, 0) argument
154 #define WCP14_DBGVCR(val) MCR14(val, 0, c0, c7, 0) argument
155 #define WCP14_DBGECR(val) MCR14(val, 0, c0, c9, 0) argument
161 #define WCP14_DBGDRCR(val) MCR14(val, 0, c0, c4, 2) argument
162 #define WCP14_DBGBVR0(val) MCR14(val, 0, c0, c0, 4) argument
163 #define WCP14_DBGBVR1(val) MCR14(val, 0, c0, c1, 4) argument
164 #define WCP14_DBGBVR2(val) MCR14(val, 0, c0, c2, 4) argument
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/arch/loongarch/include/asm/
A Dkvm_csr.h49 #define write_gcsr_crmd(val) gcsr_write(val, LOONGARCH_CSR_CRMD) argument
51 #define write_gcsr_prmd(val) gcsr_write(val, LOONGARCH_CSR_PRMD) argument
53 #define write_gcsr_euen(val) gcsr_write(val, LOONGARCH_CSR_EUEN) argument
55 #define write_gcsr_misc(val) gcsr_write(val, LOONGARCH_CSR_MISC) argument
57 #define write_gcsr_ecfg(val) gcsr_write(val, LOONGARCH_CSR_ECFG) argument
61 #define write_gcsr_era(val) gcsr_write(val, LOONGARCH_CSR_ERA) argument
63 #define write_gcsr_badv(val) gcsr_write(val, LOONGARCH_CSR_BADV) argument
75 #define write_gcsr_pgd(val) gcsr_write(val, LOONGARCH_CSR_PGD) argument
175 gcsr_xchg(val, val, LOONGARCH_CSR_ESTAT)
177 gcsr_xchg(~(val), val, LOONGARCH_CSR_ESTAT)
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A Dpercpu.h50 : [val] "r" (val)); \
56 : [val] "r" (val)); \
152 #define this_cpu_add_4(pcp, val) _percpu_add(pcp, val) argument
153 #define this_cpu_add_8(pcp, val) _percpu_add(pcp, val) argument
158 #define this_cpu_and_4(pcp, val) _percpu_and(pcp, val) argument
159 #define this_cpu_and_8(pcp, val) _percpu_and(pcp, val) argument
161 #define this_cpu_or_4(pcp, val) _percpu_or(pcp, val) argument
162 #define this_cpu_or_8(pcp, val) _percpu_or(pcp, val) argument
174 #define this_cpu_xchg_1(pcp, val) _percpu_xchg(pcp, val) argument
175 #define this_cpu_xchg_2(pcp, val) _percpu_xchg(pcp, val) argument
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/arch/mips/pci/
A Dpci-bcm63xx.c123 u32 val; in bcm63xx_reset_pcie() local
132 val = bcm_misc_readl(reg); in bcm63xx_reset_pcie()
134 bcm_misc_writel(val, reg); in bcm63xx_reset_pcie()
152 u32 val; in bcm63xx_register_pcie() local
165 val |= OPT1_RD_BE_OPT_EN; in bcm63xx_register_pcie()
178 val |= OPT2_TX_CREDIT_CHK_EN; in bcm63xx_register_pcie()
183 val |= OPT2_CFG_TYPE1_BD_SEL; in bcm63xx_register_pcie()
200 val |= BASEMASK_REMAP_EN; in bcm63xx_register_pcie()
214 u32 val; in bcm63xx_register_pci() local
272 val = 0; in bcm63xx_register_pci()
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/arch/mips/include/asm/
A Dmipsregs.h1812 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) argument
1830 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) argument
1856 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) argument
1861 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) argument
1870 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) argument
1904 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) argument
1930 #define write_c0_maar(val) __write_ulong_c0_register($17, 1, val) argument
1987 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) argument
2012 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) argument
2114 #define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val) argument
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A Dmipsmtregs.h433 #define write_vpe_c0_count(val) mttc0($9, 0, val) argument
435 #define write_vpe_c0_status(val) mttc0($12, 0, val) argument
437 #define write_vpe_c0_cause(val) mttc0($13, 0, val) argument
439 #define write_vpe_c0_config(val) mttc0($16, 0, val) argument
445 #define write_vpe_c0_ebase(val) mttc0($15, 1, val) argument
449 #define write_vpe_c0_epc(val) mttc0($14, 0, val) argument
454 #define write_tc_c0_tcstatus(val) mttc0($2, 1, val) argument
456 #define write_tc_c0_tcbind(val) mttc0($2, 2, val) argument
460 #define write_tc_c0_tchalt(val) mttc0($2, 4, val) argument
466 #define write_tc_gpr_sp(val) mttgpr($29, val) argument
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/arch/x86/virt/vmx/tdx/
A Dtdx_global_metadata.c13 u64 val; in get_tdx_sys_info_features() local
16 sysinfo_features->tdx_features0 = val; in get_tdx_sys_info_features()
24 u64 val; in get_tdx_sys_info_tdmr() local
27 sysinfo_tdmr->max_tdmrs = val; in get_tdx_sys_info_tdmr()
31 sysinfo_tdmr->pamt_4k_entry_size = val; in get_tdx_sys_info_tdmr()
43 u64 val; in get_tdx_sys_info_td_ctrl() local
46 sysinfo_td_ctrl->tdr_base_size = val; in get_tdx_sys_info_td_ctrl()
48 sysinfo_td_ctrl->tdcs_base_size = val; in get_tdx_sys_info_td_ctrl()
58 u64 val; in get_tdx_sys_info_td_conf() local
66 sysinfo_td_conf->xfam_fixed0 = val; in get_tdx_sys_info_td_conf()
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/arch/arm64/boot/dts/ti/
A Dk3-pinctrl.h72 #define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) argument
75 #define AM62DX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) argument
78 #define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) argument
81 #define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) argument
82 #define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) argument
84 #define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) argument
87 #define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) argument
90 #define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) argument
93 #define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) argument
96 #define J722S_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) argument
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/arch/s390/include/asm/
A Datomic_ops.h17 int val; in __atomic_read() local
21 : [val] "=d" (val) : [ptr] "R" (*ptr)); in __atomic_read()
27 if (__builtin_constant_p(val) && val >= S16_MIN && val <= S16_MAX) { in __atomic_set()
30 : [ptr] "=Q" (*ptr) : [val] "K" (val)); in __atomic_set()
34 : [ptr] "=R" (*ptr) : [val] "d" (val)); in __atomic_set()
44 : [val] "=d" (val) : [ptr] "RT" (*ptr)); in __atomic64_read()
50 if (__builtin_constant_p(val) && val >= S16_MIN && val <= S16_MAX) { in __atomic64_set()
53 : [ptr] "=Q" (*ptr) : [val] "K" (val)); in __atomic64_set()
57 : [ptr] "=RT" (*ptr) : [val] "d" (val)); in __atomic64_set()
185 : [val] "d" (val) \
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A Dpercpu.h44 #define this_cpu_add_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) argument
45 #define this_cpu_add_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) argument
48 #define this_cpu_and_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, &) argument
49 #define this_cpu_and_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, &) argument
50 #define this_cpu_or_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, |) argument
51 #define this_cpu_or_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, |) argument
55 #define this_cpu_add_4(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) argument
56 #define this_cpu_add_8(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) argument
59 #define this_cpu_and_4(pcp, val) arch_this_cpu_to_op_simple(pcp, val, &) argument
127 #define this_cpu_and_4(pcp, val) arch_this_cpu_to_op(pcp, val, "lan") argument
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/arch/powerpc/lib/
A Dqspinlock.c318 if (READ_ONCE(lock->val) == val) { in __yield_to_locked_owner()
392 u32 val = READ_ONCE(lock->val); in yield_to_prev() local
461 u32 val; in try_to_steal_lock() local
473 val = READ_ONCE(lock->val); in try_to_steal_lock()
530 u32 val, old, tail; in queued_spin_lock_mcs_queue() local
612 val = READ_ONCE(lock->val); in queued_spin_lock_mcs_queue()
745 steal_spins = val; in steal_spins_set()
761 steal_spins = val; in steal_spins_set()
763 steal_spins = val; in steal_spins_set()
803 head_spins = val; in head_spins_set()
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/arch/arm64/include/asm/
A Darm_pmuv3.h23 write_sysreg(val, pmevcntr##n##_el0)
30 write_sysreg(val, pmevtyper##n##_el0)
67 write_sysreg(val, pmcr_el0); in write_pmcr()
77 write_sysreg(val, pmselr_el0); in write_pmselr()
82 write_sysreg(val, pmccntr_el0); in write_pmccntr()
102 write_sysreg(val, pmcntenset_el0); in write_pmcntenset()
107 write_sysreg(val, pmcntenclr_el0); in write_pmcntenclr()
112 write_sysreg(val, pmintenset_el1); in write_pmintenset()
122 write_sysreg(val, pmccfiltr_el0); in write_pmccfiltr()
142 write_sysreg(val, pmovsclr_el0); in write_pmovsclr()
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A Dpercpu.h84 : [val] "r" ((u##sz)(val))); \
106 : [val] "r" ((u##sz)(val))); \
183 #define this_cpu_add_1(pcp, val) \ argument
185 #define this_cpu_add_2(pcp, val) \ argument
187 #define this_cpu_add_4(pcp, val) \ argument
189 #define this_cpu_add_8(pcp, val) \ argument
201 #define this_cpu_and_1(pcp, val) \ argument
203 #define this_cpu_and_2(pcp, val) \ argument
205 #define this_cpu_and_4(pcp, val) \ argument
207 #define this_cpu_and_8(pcp, val) \ argument
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/arch/mips/bcm63xx/
A Dcs.c38 u32 val; in bcm63xx_set_cs_base() local
70 u32 val; in bcm63xx_set_cs_timing() local
77 val &= ~(MPI_CSCTL_WAIT_MASK); in bcm63xx_set_cs_timing()
78 val &= ~(MPI_CSCTL_SETUP_MASK); in bcm63xx_set_cs_timing()
79 val &= ~(MPI_CSCTL_HOLD_MASK); in bcm63xx_set_cs_timing()
97 u32 val; in bcm63xx_set_cs_param() local
112 val &= ~(MPI_CSCTL_TSIZE_MASK); in bcm63xx_set_cs_param()
114 val |= params; in bcm63xx_set_cs_param()
129 u32 val; in bcm63xx_set_cs_status() local
137 val |= MPI_CSCTL_ENABLE_MASK; in bcm63xx_set_cs_status()
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/arch/alpha/include/uapi/asm/
A Dcompiler.h14 # define __kernel_insbl(val, shift) __builtin_alpha_insbl(val, shift) argument
15 # define __kernel_inswl(val, shift) __builtin_alpha_inswl(val, shift) argument
16 # define __kernel_insql(val, shift) __builtin_alpha_insql(val, shift) argument
17 # define __kernel_inslh(val, shift) __builtin_alpha_inslh(val, shift) argument
18 # define __kernel_extbl(val, shift) __builtin_alpha_extbl(val, shift) argument
19 # define __kernel_extwl(val, shift) __builtin_alpha_extwl(val, shift) argument
22 # define __kernel_insbl(val, shift) \ argument
26 # define __kernel_inswl(val, shift) \ argument
30 # define __kernel_insql(val, shift) \ argument
96 #define __kernel_stb(val,mem) ((mem) = (val)) argument
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/arch/powerpc/platforms/powernv/
A Dvas-window.c283 val = SET_FIELD(VAS_XLATE_MSR_HV, val, 1); in init_xlate_regs()
284 val = SET_FIELD(VAS_XLATE_MSR_SF, val, 1); in init_xlate_regs()
286 val = SET_FIELD(VAS_XLATE_MSR_DR, val, 1); in init_xlate_regs()
287 val = SET_FIELD(VAS_XLATE_MSR_PR, val, 1); in init_xlate_regs()
303 val = SET_FIELD(VAS_XLATE_LPCR_SC, val, 0); in init_xlate_regs()
325 val = SET_FIELD(VAS_SEIDR, val, 0); in init_xlate_regs()
489 val = SET_FIELD(VAS_PUSH_TO_MEM, val, 1); in init_winctx_regs()
502 val = SET_FIELD(VAS_WINCTL_OPEN, val, 1); in init_winctx_regs()
1266 val = SET_FIELD(VAS_WINCTL_PIN, val, 0); in unpin_close_window()
1353 val = SET_FIELD(VAS_TX_WCRED, val, 1); in vas_return_credit()
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/arch/x86/kernel/
A Dquirks.c77 u32 val; in ich_force_hpet_resume() local
100 u32 val; in ich_force_enable_hpet() local
128 val = val & 0x3; in ich_force_enable_hpet()
143 val = val & 0x3; in ich_force_enable_hpet()
190 u32 val; in old_ich_force_hpet_resume() local
212 u32 val; in old_ich_force_enable_hpet() local
287 u32 val; in vt8237_force_hpet_resume() local
304 u32 val; in vt8237_force_enable_hpet() local
435 u32 val; in nvidia_force_enable_hpet() local
544 u32 val; in quirk_amd_nb_node() local
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/arch/arm64/kvm/hyp/
A Dvgic-v3-sr.c153 u32 val; in __vgic_v3_read_ap0rn() local
172 return val; in __vgic_v3_read_ap0rn()
177 u32 val; in __vgic_v3_read_ap1rn() local
196 return val; in __vgic_v3_read_ap1rn()
326 u64 val; in __vgic_v3_deactivate_traps() local
358 u64 val; in __vgic_v3_save_aprs() local
391 u64 val; in __vgic_v3_restore_aprs() local
491 val = (val & ICC_SRE_EL1_SRE) ? 0 : (1ULL << 63); in __vgic_v3_get_gic_config()
620 u32 val; in __vgic_v3_get_highest_active_priority() local
690 u32 val; in __vgic_v3_set_active_priority() local
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/arch/sparc/kernel/
A Dpcr.c57 u64 val; in direct_pcr_read() local
61 return val; in direct_pcr_read()
72 u64 val; in direct_pic_read() local
76 return val; in direct_pic_read()
146 unsigned long val; in n4_pcr_read() local
150 return val; in n4_pcr_read()
160 unsigned long val; in n4_pic_read() local
166 return val; in n4_pic_read()
197 unsigned long val; in n5_pcr_read() local
201 return val; in n5_pcr_read()
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/arch/arc/include/asm/
A Dspinlock.h19 unsigned int val; in arch_spin_lock() local
27 : [val] "=&r" (val) in arch_spin_lock()
56 : [val] "=&r" (val), in arch_spin_trylock()
100 : [val] "=&r" (val) in arch_read_lock()
123 : [val] "=&r" (val), in arch_read_trylock()
157 : [val] "=&r" (val) in arch_write_lock()
181 : [val] "=&r" (val), in arch_write_trylock()
208 : [val] "=&r" (val) in arch_read_unlock()
236 : "+&r" (val) in arch_spin_lock()
252 : "+r" (val) in arch_spin_trylock()
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/arch/arm/mach-hisi/
A Dhotplug.c77 u32 val = 0; in set_cpu_hi3620() local
94 val |= CPU0_HPM_SRST_REQ_EN; in set_cpu_hi3620()
104 val = readl_relaxed(ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
105 val &= ~(CPU0_WFI_MASK_CFG << cpu); in set_cpu_hi3620()
106 writel_relaxed(val, ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
115 val |= (CPU0_WFI_MASK_CFG << cpu); in set_cpu_hi3620()
192 u32 val = 0; in hix5hd2_set_cpu() local
202 val |= PMC0_CPU1_PMC_ENABLE; in hix5hd2_set_cpu()
206 val &= ~CRG20_CPU1_RESET; in hix5hd2_set_cpu()
212 val &= ~PMC0_CPU1_WAIT_MTCOMS_ACK; in hix5hd2_set_cpu()
[all …]
/arch/arm64/kernel/
A Dmodule.c39 return val; in do_reloc()
41 return val - (u64)place; in do_reloc()
53 __typeof__(val) __val = (val); \
64 s64 sval = do_reloc(op, place, val); in reloc_data()
134 sval = do_reloc(op, place, val); in reloc_insn_movw()
177 sval = do_reloc(op, place, val); in reloc_insn_imm()
220 val = module_emit_veneer_for_adrp(mod, sechdrs, place, val & ~0xfff); in reloc_insn_adrp()
221 if (!val) in reloc_insn_adrp()
242 u64 val; in apply_relocate_add() local
255 val = sym->st_value + rel[i].r_addend; in apply_relocate_add()
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/arch/x86/kernel/cpu/mce/
A Dintel.c141 u64 val; in cmci_set_threshold() local
209 return val; in cmci_pick_threshold()
213 val |= CMCI_THRESHOLD; in cmci_pick_threshold()
221 val |= CMCI_THRESHOLD; in cmci_pick_threshold()
224 return val; in cmci_pick_threshold()
234 val |= MCI_CTL2_CMCI_EN; in cmci_claim_bank()
285 u64 val; in cmci_discover() local
291 val = cmci_pick_threshold(val, &bios_zero_thresh); in cmci_discover()
323 u64 val; in __cmci_disable_bank() local
428 u64 val; in intel_init_lmce() local
[all …]
/arch/x86/include/asm/
A Dqspinlock.h16 u32 val; in queued_fetch_set_pending_acquire() local
23 val = GEN_BINARY_RMWcc(LOCK_PREFIX "btsl", lock->val.counter, c, in queued_fetch_set_pending_acquire()
25 val |= atomic_read(&lock->val) & ~_Q_PENDING_MASK; in queued_fetch_set_pending_acquire()
27 return val; in queued_fetch_set_pending_acquire()
31 extern void native_queued_spin_lock_slowpath(struct qspinlock *lock, u32 val);
33 extern void __pv_queued_spin_lock_slowpath(struct qspinlock *lock, u32 val);
49 static inline void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val) in queued_spin_lock_slowpath() argument
51 pv_queued_spin_lock_slowpath(lock, val); in queued_spin_lock_slowpath()
90 int val; in virt_spin_lock() local
102 val = atomic_read(&lock->val); in virt_spin_lock()
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