| /arch/mips/cavium-octeon/ |
| A D | octeon-memcpy.S | 90 #define ADD daddu macro
289 ADD src, src, NBYTES
299 ADD src, src, NBYTES
307 ADD src, src, NBYTES
400 ADD src, src, 1
403 ADD dst, dst, 1
436 ADD len, len, 1
444 ADD t0, a0, a2
445 ADD t1, a1, a2
478 ADD a1, a1, 0x1
[all …]
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| /arch/mips/lib/ |
| A D | memcpy.S | 192 #define ADD addu macro
435 ADD dst, dst, t2
534 ADD src, src, 8
536 ADD dst, dst, 8
560 ADD src, src, 1
563 ADD dst, dst, 1
593 ADD len, len, 1
605 ADD t0, a0, a2
606 ADD t1, a1, a2
643 ADD a1, a1, 0x1
[all …]
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| A D | csum_partial.S | 45 #define ADD daddu macro
52 #define ADD addu macro
62 ADD sum, reg; \
64 ADD sum, v1; \
380 #define ADD daddu macro
400 #define ADD addu macro
542 ADD src, src, NBYTES
547 ADD dst, dst, NBYTES
588 ADD t2, zero, NBYTES
599 ADD dst, dst, t2
[all …]
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| /arch/arm/kernel/ |
| A D | phys2virt.S | 155 @ In the non-LPAE case, all patchable instructions are ADD or SUB
163 @ ADD | cond | 0 0 1 0 1 0 0 0 | Rn | Rd | imm12 |
173 @ instructions based on bits 23:22 of the opcode, and ADD/SUB can be
189 tst ip, #PV_BIT24 @ ADD/SUB have bit 24 clear
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| /arch/sparc/net/ |
| A D | bpf_jit_comp_32.c | 73 #define ADD F3(2, 0x00) macro
280 *prog++ = (ADD | RS1(R1) | RS2(R2) | RD(R3))
283 *prog++ = (ADD | IMMED | RS1(R1) | S13(IMM) | RD(R3))
295 *prog++ = (ADD | IMMED | RS1(SP) | S13(SZ) | RD(SP))
400 emit_alu_X(ADD); in bpf_jit_compile()
403 emit_alu_K(ADD, K); in bpf_jit_compile()
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| A D | bpf_jit_comp_64.c | 141 #define ADD F3(2, 0x00) macro
826 emit(ADD | IMMED | RS1(FP) | S13(STACK_BIAS) | RD(vfp), ctx); in build_prologue()
873 emit_alu_K(ADD, tmp, 1, ctx); in emit_tail_call()
878 emit_alu(ADD, bpf_array, tmp, ctx); in emit_tail_call()
920 emit_alu(ADD, src, dst, ctx); in build_insn()
1056 emit_alu3_K(ADD, SP, STACK_BIAS + 128, tmp, ctx); in build_insn()
1075 emit_alu_K(ADD, dst, imm, ctx); in build_insn()
1391 emit_alu3(ADD, dst, tmp, tmp, ctx); in build_insn()
1394 emit_alu3(ADD, tmp2, src, tmp3, ctx); in build_insn()
1419 emit_alu3(ADD, dst, tmp, tmp, ctx); in build_insn()
[all …]
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| /arch/arm64/net/ |
| A D | bpf_jit.h | 153 #define A64_STADD(sf, Rn, Rs) A64_ST_OP(sf, Rn, Rs, ADD)
163 #define A64_LDADDAL(sf, Rt, Rn, Rs) A64_LD_OP_AL(sf, Rt, Rn, Rs, ADD)
179 #define A64_ADD_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, ADD)
236 #define A64_ADD(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, ADD)
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| /arch/x86/lib/ |
| A D | x86-opcode-map.txt | 46 00: ADD Eb,Gb
47 01: ADD Ev,Gv
48 02: ADD Gb,Eb
49 03: ADD Gv,Ev
50 04: ADD AL,Ib
51 05: ADD rAX,Iz
936 00: ADD Eb,Gb (ev)
937 01: ADD Ev,Gv (es) | ADD Ev,Gv (66),(es)
938 02: ADD Gb,Eb (ev)
939 03: ADD Gv,Ev (es) | ADD Gv,Ev (66),(es)
[all …]
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| /arch/arm/boot/dts/microchip/ |
| A D | at91-tse850-3.dts | 308 /* 8 */ "/ADD", "", "/LOOP1", "/LOOP2",
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| /arch/arc/include/asm/ |
| A D | entry-arcv2.h | 168 ; ISA requires ADD.nz to have same dest and src reg operands
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| /arch/m68k/fpsp040/ |
| A D | round.S | 191 | ADD SINGLE
209 | ADD EXTENDED
228 | ADD DOUBLE
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| A D | slogn.S | 418 faddx KLOG2(%a6),%fp0 | ...FINAL ADD
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| /arch/sh/math-emu/ |
| A D | math.c | 110 BOTH_PRmn(ARITH_X, ADD); in fadd()
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| /arch/m68k/ifpsp060/src/ |
| A D | fplsp.S | 7410 mov.b &FADD_OP,%d1 # last inst is ADD
7641 mov.b &FADD_OP,%d1 # last inst is ADD
7932 mov.b &FADD_OP,%d1 # last inst is ADD
8315 fadd.x KLOG2(%a6),%fp0 # FINAL ADD
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| A D | fpsp.S | 14658 # ADD: norms and denorms
|