Searched refs:ASID (Results 1 – 14 of 14) sorted by relevance
| /arch/arm/include/asm/ |
| A D | mmu.h | 27 #define ASID(mm) ((unsigned int)((mm)->context.id.counter & ~ASID_MASK)) macro
29 #define ASID(mm) (0) macro
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| A D | tlbflush.h | 363 const int asid = ASID(mm); in __local_flush_tlb_mm()
381 const int asid = ASID(mm); in local_flush_tlb_mm()
405 tlb_op(TLB_V7_UIS_ASID, "c8, c3, 2", ASID(mm)); in __flush_tlb_mm()
418 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); in __local_flush_tlb_page()
439 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); in local_flush_tlb_page()
456 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); in __flush_tlb_page()
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| /arch/arm/mm/ |
| A D | tlb-v7.S | 41 asid r3, r3 @ mask ASID
50 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
79 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
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| A D | tlb-v6.S | 43 asid r3, r3 @ mask ASID
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| A D | Kconfig | 610 This indicates whether the CPU has the ASID register; used to
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| /arch/arm64/include/asm/ |
| A D | mmu.h | 57 #define ASID(mm) (atomic64_read(&(mm)->context.id) & 0xffff) macro
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| A D | tlbflush.h | 278 asid = __TLBI_VADDR(0, ASID(mm)); in flush_tlb_mm()
291 addr = __TLBI_VADDR(uaddr, ASID(mm)); in __flush_tlb_page_nosync()
453 asid = ASID(mm); in __flush_tlb_range_nosync()
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| A D | mmu_context.h | 221 ttbr = phys_to_ttbr(virt_to_phys(mm->pgd)) | ASID(mm) << 48; in update_saved_ttbr0()
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| /arch/loongarch/include/asm/ |
| A D | hw_breakpoint.h | 54 #define LOONGARCH_CSR_NAME_ASID ASID
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| /arch/loongarch/kernel/ |
| A D | hw_breakpoint.c | 86 GEN_READ_WB_REG_CASES(CSR_CFG_ASID, ASID, t, val); in read_wb_reg()
101 GEN_WRITE_WB_REG_CASES(CSR_CFG_ASID, ASID, t, val); in write_wb_reg()
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| /arch/arm64/mm/ |
| A D | context.c | 352 unsigned long asid = ASID(mm); in cpu_do_switch_mm()
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| /arch/arm/ |
| A D | Kconfig | 650 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
654 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
659 entries regardless of the ASID.
693 bool "ARM errata: possible faulty MMU translations following an ASID switch"
698 which starts prior to an ASID switch but completes afterwards. This
700 the new ASID. This workaround places two dsb instructions in the mm
701 switching code so that no page table walks can cross the ASID switch.
768 which sends an IPI to the CPUs that are running the same ASID
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| /arch/arm64/ |
| A D | Kconfig | 1200 contains data for a non-current ASID. The fix is to
1274 bool "Falkor E1003: Incorrect translation due to ASID change"
1277 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1278 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1722 zeroed area and reserved ASID. The user access routines
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| /arch/arm64/tools/ |
| A D | sysreg | 4716 Field 63:48 ASID
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