Searched refs:Add (Results 1 – 25 of 48) sorted by relevance
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65 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode73 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode80 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode87 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode94 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode101 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode108 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode115 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode
19 Add support for old Broadcom BCM47xx boards with Sonics Silicon Backplane support.36 Add support for new Broadcom BCM47xx boards with Broadcom specific Advanced Microcontroller Bus.
3 * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with4 * J784S4 EVM. The Add-On Ethernet Card has to be connected to ENET Expansion 1 slot on the
3 * DT Overlay for CPSW5G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
3 * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
17 /* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */
8 Add checks with low performance impact to the spinlock functions
20 Add extra files to (debugfs)/ras/cec to test the correctable error
57 * Add the phy clock here, so the phy can be accessed to read its
178 * Add SPI CS pins for clearfog:
230 * Add SPI CS pins for clearfog:
35 | A5. Add using the carry the 64-bit quantities in d2:d3 and d4:d5102 | A5. Add mul by 8 to mul by 2. D1 contains the digit formed.
93 | Source is positive. Add the src to the dest exponent.142 | Source is negative. Add the src to the dest exponent.
15 * REVISIT: Add timing support from slls644g.pdf
82 addq v0, a2, v0 # E : Add in the bit number from above
55 Add a number of spare GPIO entries between each bank for debugging
142 /* TODO: Add regulators once PMIC is implemented */
156 /* Add legacy interrupts for SATA devices only */
240 /* Add pinmux for rts-gpios (uart5_rts_pin) */
138 /* Add pullup to DATA line */
583 Add support for pointer masking in userspace (Supm) when the614 Add support for the Svpbmt ISA-extension (Supervisor-mode:640 Add support for the Vector extension when it is detected at boot.753 Add support for enabling optimisations in the kernel when the Zba766 Add support for enabling optimisations in the kernel when the829 Add support for the Zicbom extension (Cache Block Management897 Add support for floating point operations when an FPU is detected at909 Add independent irq & softirq stacks for percpu to prevent kernel stack
11 * fpa11.h - Add documentation
109 * Add the calibration PHYs for SATA here, although only
101 * Add some discrete steps to help throttling system deal
1381 #define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \ argument1382 (((Add) - 9) << FShft (MDCNFG_DRAC))
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