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/arch/sh/kernel/cpu/sh4/
A Dperf_event.c91 [ C(L1D) ] = {
92 [ C(OP_READ) ] = {
106 [ C(L1I) ] = {
107 [ C(OP_READ) ] = {
121 [ C(LL) ] = {
122 [ C(OP_READ) ] = {
136 [ C(DTLB) ] = {
137 [ C(OP_READ) ] = {
151 [ C(ITLB) ] = {
166 [ C(BPU) ] = {
[all …]
/arch/sh/kernel/cpu/sh4a/
A Dperf_event.c116 [ C(L1D) ] = {
117 [ C(OP_READ) ] = {
131 [ C(L1I) ] = {
132 [ C(OP_READ) ] = {
146 [ C(LL) ] = {
147 [ C(OP_READ) ] = {
161 [ C(DTLB) ] = {
162 [ C(OP_READ) ] = {
176 [ C(ITLB) ] = {
191 [ C(BPU) ] = {
[all …]
/arch/x86/events/zhaoxin/
A Dcore.c52 [C(L1D)] = {
66 [C(L1I)] = {
80 [C(LL)] = {
94 [C(DTLB)] = {
108 [C(ITLB)] = {
122 [C(BPU)] = {
136 [C(NODE)] = {
156 [C(L1D)] = {
170 [C(L1I)] = {
184 [C(LL)] = {
[all …]
/arch/x86/events/intel/
A Dp6.c31 [ C(L1D) ] = {
32 [ C(OP_READ) ] = {
36 [ C(OP_WRITE) ] = {
45 [ C(L1I ) ] = {
46 [ C(OP_READ) ] = {
59 [ C(LL ) ] = {
60 [ C(OP_READ) ] = {
73 [ C(DTLB) ] = {
74 [ C(OP_READ) ] = {
87 [ C(ITLB) ] = {
[all …]
A Dknc.c27 [ C(L1D) ] = {
28 [ C(OP_READ) ] = {
37 [ C(OP_WRITE) ] = {
46 [ C(L1I ) ] = {
47 [ C(OP_READ) ] = {
60 [ C(LL ) ] = {
61 [ C(OP_READ) ] = {
74 [ C(DTLB) ] = {
75 [ C(OP_READ) ] = {
90 [ C(ITLB) ] = {
[all …]
A Dcore.c1940 [C(LL)] = {
2002 [C(LL)] = {
2056 [C(LL)] = {
2118 [C(LL)] = {
6821 hybrid_var(pmu, hw_cache_event_ids)[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init_grt()
7112 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init()
7325 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | in intel_pmu_init()
7327 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| in intel_pmu_init()
7329 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| in intel_pmu_init()
7331 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| in intel_pmu_init()
[all …]
/arch/powerpc/perf/
A Dpower10-pmu.c358 static u64 power10_cache_events_dd1[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
359 [C(L1D)] = {
373 [C(L1I)] = {
387 [C(LL)] = {
429 [C(BPU)] = {
459 static u64 power10_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
460 [C(L1D)] = {
474 [C(L1I)] = {
488 [C(LL)] = {
530 [C(BPU)] = {
[all …]
A Dgeneric-compat-pmu.c185 static u64 generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
186 [ C(L1D) ] = {
187 [ C(OP_READ) ] = {
200 [ C(L1I) ] = {
201 [ C(OP_READ) ] = {
214 [ C(LL) ] = {
228 [ C(DTLB) ] = {
242 [ C(ITLB) ] = {
256 [ C(BPU) ] = {
270 [ C(NODE) ] = {
[all …]
A Dpower8-pmu.c266 static u64 power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
267 [ C(L1D) ] = {
268 [ C(OP_READ) ] = {
281 [ C(L1I) ] = {
282 [ C(OP_READ) ] = {
295 [ C(LL) ] = {
309 [ C(DTLB) ] = {
323 [ C(ITLB) ] = {
337 [ C(BPU) ] = {
351 [ C(NODE) ] = {
[all …]
A De6500-pmu.c35 static int e6500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
36 [C(L1D)] = {
38 [C(OP_READ)] = { 27, 222 },
42 [C(L1I)] = {
44 [C(OP_READ)] = { 2, 254 },
53 [C(LL)] = {
55 [C(OP_READ)] = { 0, 0 },
56 [C(OP_WRITE)] = { 0, 0 },
65 [C(DTLB)] = {
71 [C(BPU)] = {
[all …]
A De500-pmu.c34 static int e500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
40 [C(OP_READ)] = { 27, 0 },
41 [C(OP_WRITE)] = { 28, 0 },
45 [C(OP_READ)] = { 2, 60 },
46 [C(OP_WRITE)] = { -1, -1 },
47 [C(OP_PREFETCH)] = { 0, 0 },
56 [C(OP_READ)] = { 0, 0 },
57 [C(OP_WRITE)] = { 0, 0 },
67 [C(OP_READ)] = { 26, 66 },
68 [C(OP_WRITE)] = { -1, -1 },
[all …]
A Dpower9-pmu.c337 static u64 power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
338 [ C(L1D) ] = {
339 [ C(OP_READ) ] = {
352 [ C(L1I) ] = {
353 [ C(OP_READ) ] = {
366 [ C(LL) ] = {
380 [ C(DTLB) ] = {
394 [ C(ITLB) ] = {
408 [ C(BPU) ] = {
422 [ C(NODE) ] = {
[all …]
A Dmpc7450-pmu.c365 static u64 mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
367 [C(OP_READ)] = { 0, 0x225 },
369 [C(OP_PREFETCH)] = { 0, 0 },
373 [C(OP_WRITE)] = { -1, -1 },
377 [C(OP_READ)] = { 0, 0 },
378 [C(OP_WRITE)] = { 0, 0 },
383 [C(OP_WRITE)] = { -1, -1 },
388 [C(OP_WRITE)] = { -1, -1 },
393 [C(OP_WRITE)] = { -1, -1 },
397 [C(OP_READ)] = { -1, -1 },
[all …]
A Dpower7-pmu.c339 static u64 power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
346 [C(OP_READ)] = { 0, 0x200fc },
347 [C(OP_WRITE)] = { -1, -1 },
353 [C(OP_PREFETCH)] = { 0, 0 },
356 [C(OP_READ)] = { 0, 0x300fc },
357 [C(OP_WRITE)] = { -1, -1 },
358 [C(OP_PREFETCH)] = { -1, -1 },
362 [C(OP_WRITE)] = { -1, -1 },
367 [C(OP_WRITE)] = { -1, -1 },
371 [C(OP_READ)] = { -1, -1 },
[all …]
A Dppc970-pmu.c438 static u64 ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
445 [C(OP_READ)] = { 0, 0 },
446 [C(OP_WRITE)] = { -1, -1 },
447 [C(OP_PREFETCH)] = { 0, 0 },
450 [C(OP_READ)] = { 0, 0 },
451 [C(OP_WRITE)] = { 0, 0 },
456 [C(OP_WRITE)] = { -1, -1 },
461 [C(OP_WRITE)] = { -1, -1 },
466 [C(OP_WRITE)] = { -1, -1 },
470 [C(OP_READ)] = { -1, -1 },
[all …]
A Dpower6-pmu.c499 static u64 power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
507 [C(OP_WRITE)] = { -1, -1 },
516 [C(OP_READ)] = { 0, 0x20000e },
517 [C(OP_WRITE)] = { -1, -1 },
518 [C(OP_PREFETCH)] = { -1, -1 },
521 [C(OP_READ)] = { 0, 0x420ce },
522 [C(OP_WRITE)] = { -1, -1 },
523 [C(OP_PREFETCH)] = { -1, -1 },
527 [C(OP_WRITE)] = { -1, -1 },
531 [C(OP_READ)] = { -1, -1 },
[all …]
A Dpower5-pmu.c567 static u64 power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
574 [C(OP_READ)] = { 0, 0 },
575 [C(OP_WRITE)] = { -1, -1 },
576 [C(OP_PREFETCH)] = { 0, 0 },
579 [C(OP_READ)] = { 0, 0x3c309b },
580 [C(OP_WRITE)] = { 0, 0 },
585 [C(OP_WRITE)] = { -1, -1 },
590 [C(OP_WRITE)] = { -1, -1 },
595 [C(OP_WRITE)] = { -1, -1 },
599 [C(OP_READ)] = { -1, -1 },
[all …]
A Dpower5+-pmu.c625 static u64 power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
632 [C(OP_READ)] = { 0, 0 },
633 [C(OP_WRITE)] = { -1, -1 },
634 [C(OP_PREFETCH)] = { 0, 0 },
637 [C(OP_READ)] = { 0, 0 },
638 [C(OP_WRITE)] = { 0, 0 },
643 [C(OP_WRITE)] = { -1, -1 },
648 [C(OP_WRITE)] = { -1, -1 },
653 [C(OP_WRITE)] = { -1, -1 },
657 [C(OP_READ)] = { -1, -1 },
[all …]
/arch/sparc/kernel/
A Dperf_event.c221 [C(L1D)] = {
235 [C(L1I)] = {
249 [C(LL)] = {
291 [C(BPU)] = {
359 [C(L1D)] = {
373 [C(L1I)] = {
387 [C(LL)] = {
429 [C(BPU)] = {
494 [C(L1D)] = {
522 [C(LL)] = {
[all …]
/arch/mips/kernel/
A Dperf_event_mipsxx.c1009 [C(L1D)] = {
1025 [C(L1I)] = {
1042 [C(LL)] = {
1072 [C(BPU)] = {
1090 [C(L1D)] = {
1106 [C(L1I)] = {
1123 [C(LL)] = {
1148 [C(BPU)] = {
1283 [C(LL)] = {
1345 [C(LL)] = {
[all …]
/arch/x86/events/amd/
A Dcore.c32 [ C(L1D) ] = {
46 [ C(L1I ) ] = {
60 [ C(LL ) ] = {
74 [ C(DTLB) ] = {
136 [C(L1D)] = {
150 [C(L1I)] = {
164 [C(LL)] = {
178 [C(DTLB)] = {
192 [C(ITLB)] = {
206 [C(BPU)] = {
[all …]
/arch/arc/kernel/
A Dperf_event.c80 static const unsigned int arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
81 [C(L1D)] = {
82 [C(OP_READ)] = {
95 [C(L1I)] = {
96 [C(OP_READ)] = {
109 [C(LL)] = {
110 [C(OP_READ)] = {
123 [C(DTLB)] = {
138 [C(ITLB)] = {
152 [C(BPU)] = {
[all …]
/arch/csky/kernel/
A Dperf_event.c729 static const int csky_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
730 [C(L1D)] = {
732 [C(OP_READ)] = {
745 [C(OP_READ)] = {
759 [C(L1I)] = {
760 [C(OP_READ)] = {
773 [C(LL)] = {
802 [C(DTLB)] = {
827 [C(ITLB)] = {
848 [C(BPU)] = {
[all …]
/arch/arm/mach-omap1/
A Dmux.c34 MUX_CFG("UART2_TX", C, 27, 1, 3, 3, 0, NA, 0, 0)
35 MUX_CFG("UART2_RX", C, 18, 0, 3, 1, 1, NA, 0, 0)
36 MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0)
37 MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0)
78 MUX_CFG("USB2_VM", C, 18, 1, 3, 0, 0, NA, 0, 1)
79 MUX_CFG("USB2_RCV", C, 21, 1, 3, 1, 0, NA, 0, 1)
80 MUX_CFG("USB2_SE0", C, 24, 2, 3, 2, 0, NA, 0, 1)
81 MUX_CFG("USB2_TXD", C, 27, 2, 3, 3, 0, NA, 0, 1)
117 MUX_CFG("MCBSP2_DR", C, 0, 0, 2, 26, 1, NA, 0, 1)
118 MUX_CFG("MCBSP2_DX", C, 15, 0, 2, 31, 1, NA, 0, 1)
[all …]
/arch/loongarch/kernel/
A Dperf_event.c676 [C(L1D)] = {
683 [C(OP_READ)] = {
696 [C(L1I)] = {
697 [C(OP_READ)] = {
702 [C(LL)] = {
703 [C(OP_READ)] = {
712 [C(ITLB)] = {
713 [C(OP_READ)] = {
717 [C(DTLB)] = {
718 [C(OP_READ)] = {
[all …]

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