| /arch/arm/boot/dts/st/ |
| A D | ste-dbx5x0-pinctrl.dtsi | 272 "GPIO24_AB2", /* CMD */
292 "GPIO24_AB2", /* CMD */
320 "GPIO24_AB2", /* CMD */
333 "GPIO24_AB2", /* CMD */
364 "GPIO210_AJ15", /* CMD */
381 "GPIO210_AJ15", /* CMD */
401 "GPIO210_AJ15", /* CMD */
444 "GPIO129_B4", /* CMD */
469 "GPIO129_B4", /* CMD */
490 "GPIO129_B4"; /* CMD */
[all …]
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| A D | stm32f7-pinctrl.dtsi | 242 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
260 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
273 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1 CMD */
284 <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
302 pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
315 <STM32_PINMUX('D', 7, ANALOG)>; /* SDMMC2 CMD */
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| A D | spear300.dtsi | 37 0x80010000 0x0010>; /* NAND Base CMD */
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| A D | spear310.dtsi | 32 0x40010000 0x0010>; /* NAND Base CMD */
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| A D | spear320.dtsi | 39 0x50010000 0x0010>; /* NAND Base CMD */
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| A D | spear600.dtsi | 79 0xd2010000 0x0010>; /* NAND Base CMD */
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| A D | spear13xx.dtsi | 142 0xb0810000 0x0010>; /* NAND Base CMD */
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| /arch/arm64/boot/dts/amlogic/ |
| A D | meson-gxl-s905x-khadas-vim.dts | 186 "eMMC Clk", "eMMC Reset", "eMMC CMD",
189 "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
198 "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD",
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| A D | meson-gxbb-nanopi-k2.dts | 262 "eMMC Reset", "eMMC CMD",
266 "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
285 "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD",
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| A D | meson-gxl-s905x-libretech-cc.dts | 274 "eMMC Clk", "eMMC Reset", "eMMC CMD",
277 "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
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| A D | meson-gxbb-odroidc2.dts | 304 "eMMC Reset", "eMMC CMD",
307 "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
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| /arch/arm64/boot/dts/freescale/ |
| A D | fsl-lx2162a-sr-som.dtsi | 40 /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
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| A D | fsl-lx2160a-cex7.dtsi | 172 /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
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| A D | imx95-phycore-fpsc.dtsi | 565 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e /* CMD */
579 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e /* CMD */
592 IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe /* CMD */
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| A D | fsl-ls1028a-kontron-sl28.dts | 123 /* The following setting enables 1-1-2 (CMD-ADDR-DATA) mode */
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| A D | fsl-ls1028a-rdb.dts | 184 /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
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| /arch/arm/boot/dts/allwinner/ |
| A D | sun8i-h2-plus-bananapi-m2-zero.dts | 234 "SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3",
241 "WL-SDIO-CLK", "WL-SDIO-CMD", "WL-SDIO-D0", "WL-SDIO-D1",
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| A D | sun6i-a31s-sinovoip-bpi-m2.dts | 281 "", "", "", "", "", "", "WL-SDIO-CMD", "WL-SDIO-CLK",
302 "SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3",
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| /arch/powerpc/include/asm/ |
| A D | cpm1.h | 45 #define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) argument
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| /arch/arm64/boot/dts/mediatek/ |
| A D | mt7622-rfb1.dts | 277 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
421 * DAT2, DAT3, CMD, CLK for SD respectively.
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| A D | mt7622-bananapi-bpi-r64.dts | 338 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
487 * DAT2, DAT3, CMD, CLK for SD respectively.
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| /arch/arm/boot/dts/microchip/ |
| A D | at91-sam9x60_curiosity.dts | 398 …AT91_PIOA 16 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA16 CMD per…
415 …AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA12 CMD per…
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| A D | at91-sam9x60ek.dts | 525 …AT91_PIOA 16 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA16 CMD per…
541 …AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA12 CMD per…
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| /arch/arm/boot/dts/intel/ixp/ |
| A D | intel-ixp42x-gateworks-gw2348.dts | 100 /* First register set is CMD second is CTL (notice it uses CS2) */
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| /arch/arm64/boot/dts/allwinner/ |
| A D | sun50i-h6-pine-h64.dts | 303 * The CS pin is shared with the MMC2 CMD pin, so we cannot have the SPI
|