Searched refs:CP (Results 1 – 24 of 24) sorted by relevance
| /arch/arm/nwfpe/ |
| A D | entry.S | 152 ret lr @ CP#0
155 ret lr @ CP#3
156 ret lr @ CP#4
157 ret lr @ CP#5
158 ret lr @ CP#6
159 ret lr @ CP#7
160 ret lr @ CP#8
161 ret lr @ CP#9
162 ret lr @ CP#10 (VFP)
164 ret lr @ CP#12
[all …]
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| /arch/arm64/boot/dts/marvell/ |
| A D | armada-8020.dtsi | 13 * in CP master is not connected (by package) to the oscillator. So
14 * disable it. However, the RTC clock in CP slave is connected to the
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| A D | armada-8040.dtsi | 21 * in CP master is not connected (by package) to the oscillator. So
22 * disable it. However, the RTC clock in CP slave is connected to the
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| A D | armada-80x0.dtsi | 61 /* The 80x0 has two CP blocks, but uses only one block from each. */
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| A D | armada-ap80x.dtsi | 316 * Only one thermal zone per AP/CP may trigger interrupts at a time, the
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| /arch/arm/boot/dts/arm/ |
| A D | integratorcp.dts | 3 * Device Tree for the ARM Integrator/CP platform
10 model = "ARM Integrator/CP";
44 * The Integrator/CP overall clocking architecture can be found in
238 * the same interrupts in all Integrators, but in the CP
272 * These PrimeCells are only available on the Integrator/CP
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| /arch/arm/boot/dts/ti/omap/ |
| A D | am57xx-beagle-x15-revc.dts | 13 gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */
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| A D | am57xx-beagle-x15-revb1.dts | 13 gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */
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| A D | am57xx-beagle-x15.dts | 14 gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */
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| A D | omap5-uevm.dts | 186 gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>, /* TCA6424A P01, CT CP HPD */
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| A D | dra76-evm.dts | 177 gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>, /* gpio7_30, CT CP HPD */
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| A D | omap4-panda-common.dtsi | 196 gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */
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| A D | dra72-evm-common.dtsi | 123 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
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| A D | omap4-sdp.dts | 170 gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */
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| /arch/s390/kernel/ |
| A D | sthyi.c | 30 #define CP 0xc3d7404040404040UL macro
239 case CP: in fill_diag_mac()
270 case CP: in lpar_cpu_inf()
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| /arch/arm/mm/ |
| A D | proc-xsc3.S | 426 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
444 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
467 mcr p15, 0, r0, c15, c1, 0 @ write CP access register
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| A D | proc-mohawk.S | 354 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
372 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
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| A D | proc-xscale.S | 516 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
532 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
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| /arch/xtensa/kernel/ |
| A D | coprocessor.S | 196 addx4 a0, a3, a0 # entry for CP
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| /arch/arm/mach-versatile/ |
| A D | Kconfig | 119 bool "Support Integrator/CP platform"
126 Include support for the ARM(R) Integrator CP platform.
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| /arch/arm/mach-pxa/ |
| A D | sleep.S | 130 @ other CP registers instead.
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| /arch/arm/boot/dts/samsung/ |
| A D | exynos4210-universal_c210.dts | 497 cp32khz_reg: EN32KHz-CP {
498 regulator-name = "32KHz CP";
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| A D | s5pv210-aries.dtsi | 403 cp32khz_reg: EN32KHz-CP {
404 regulator-name = "32KHz CP";
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| A D | exynos4412-p4note.dtsi | 891 /* 0 = CP, 1 = AP (serial output) */
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