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Searched refs:Control (Results 1 – 25 of 46) sorted by relevance

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/arch/powerpc/sysdev/
A DKconfig31 This option enables support for RCPM (Run Control/Power Management).
/arch/arm/boot/dts/intel/ixp/
A Dintel-ixp46x-ixdp465.dts3 * Device Tree file for the Intel IXDP465 Control Plane processor reference
A Dintel-ixp43x-kixrp435.dts3 * Device Tree file for the Intel KIXRP435 Control Plane
A Dintel-ixp42x-ixdp425.dts3 * Device Tree file for the Intel IXDP425 also known as IXCDP1100 Control Plane
/arch/arm/boot/dts/aspeed/
A Daspeed-bmc-facebook-cmm.dts49 * channels are connecting to 4 Fan Control Boards.
229 * PCA9548 (32-0070), 8 channels connecting to Fan Control
242 * PCA9548 (33-0070), 8 channels connecting to Fan Control
255 * PCA9548 (34-0070), 8 channels connecting to Fan Control
268 * PCA9548 (35-0070), 8 channels connecting to Fan Control
1279 * I2C bus to Fan Control Boards.
1291 /* To Fan Control Board #1 */
1347 /* To Fan Control Board #2 */
1403 /* To Fan Control Board #3 */
1459 /* To Fan Control Board #4 */
A Daspeed-bmc-facebook-minipack.dts102 * connecting to top FCM (Fan Control Module).
115 * connecting to bottom FCM (Fan Control Module).
569 * (Fan Control Module).
635 * FCM (Fan Control Module).
/arch/powerpc/platforms/52xx/
A Dlite5200_pm.c175 out_be32(&bes->Control, sbes.Control); in lite5200_restore_regs()
/arch/arm/common/
A Dvlock.S61 @ Control dependency implies strb not observable before previous ldrb.
A Dmcpm_head.S118 @ Control dependency implies strb not observable before previous ldrb.
/arch/x86/platform/olpc/
A Dxo1-wakeup.S35 # Control registers were modified, pipeline resync is needed
/arch/arm64/boot/dts/mediatek/
A Dmt8186-corsola-chinchou.dtsi194 MATRIX_KEY(0x01, 0x0e, KEY_LEFTCTRL) /* Left Control*/
196 MATRIX_KEY(0x03, 0x0e, KEY_RIGHTCTRL) /* Right Control*/
/arch/arm64/boot/dts/exynos/
A Dexynos850-pinctrl.dtsi225 /* USI_CMGP0: UART function (4 pins, Auto Flow Control) */
232 /* USI_CMGP0: UART function (2 pins, Non-Auto Flow Control) */
255 /* USI_CMGP1: UART function (4 pins, Auto Flow Control) */
262 /* USI_CMGP1: UART function (2 pins, Non-Auto Flow Control) */
/arch/arm/boot/dts/actions/
A Dowl-s500.dtsi265 <0xb01b0040 0x10>, /* Multiplexing Control */
266 <0xb01b0060 0x18>, /* PAD Control */
/arch/arm64/boot/dts/ti/
A Dk3-am65-mcu.dtsi292 ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */
293 <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */
294 <0x0 0x47050000 0x0 0x47050000 0x0 0x100>, /* OSPI1 Control */
A Dk3-j721e-mcu-wakeup.dtsi358 ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */
359 <0x0 0x47034000 0x0 0x47034000 0x0 0x100>, /* HBMC Control */
360 <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */
361 <0x0 0x47050000 0x0 0x47050000 0x0 0x100>, /* OSPI1 Control */
A Dk3-j7200-mcu-wakeup.dtsi543 ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */
544 <0x0 0x47034000 0x0 0x47040000 0x0 0x100>, /* HBMC Control */
545 <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */
A Dk3-j784s4-j742s2-mcu-wakeup-common.dtsi683 ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00000100>, /* FSS Control */
684 <0x00 0x47040000 0x00 0x47040000 0x00 0x00000100>, /* OSPI0 Control */
685 <0x00 0x47050000 0x00 0x47050000 0x00 0x00000100>, /* OSPI1 Control */
/arch/powerpc/boot/dts/fsl/
A De500mc_power_isa.dtsi48 power-isa-e.pc; // Embedded.Processor Control
A De5500_power_isa.dtsi48 power-isa-e.pc; // Embedded.Processor Control
A De6500_power_isa.dtsi48 power-isa-e.pc; // Embedded.Processor Control
/arch/parisc/include/asm/
A Dasmregs.h115 ;! Control Registers
/arch/powerpc/include/asm/
A Dmpc52xx.h101 u32 Control; /* SDMA + 0x78 */ member
/arch/arm/nwfpe/
A Dentry.S167 ret lr @ CP#15 (Control)
/arch/arm/mm/
A Dproc-v7m.S156 @ Configure the System Control Register to ensure 8-byte stack alignment
/arch/m68k/hp300/
A Dhp300map.map19 keycode 6 = Control

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