| /arch/mips/cavium-octeon/ |
| A D | octeon-memcpy.S | 187 EXC( LOAD t0, UNIT(0)(src), l_exc)
235 EXC( LOAD t0, UNIT(0)(src), l_exc)
262 EXC( LOAD t0, UNIT(0)(src), l_exc)
285 EXC( LOAD t0, 0(src), l_exc)
288 EXC( STORE t0, 0(dst), s_exc_p1u)
295 EXC( LOAD t0, 0(src), l_exc)
305 EXC( LOAD t0, 0(src), l_exc)
361 EXC( lb t0, N(src), l_exc); \
364 EXC( sb t0, N(dst), s_exc_p1)
372 EXC( lb t0, NBYTES-2(src), l_exc)
[all …]
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| /arch/sh/lib/ |
| A D | checksum.S | 153 #define EXC(...) \ macro
195 EXC( mov.b @r4+,r1 )
198 EXC( mov.b r1,@r5 )
229 EXC( mov.w r0,@r5 )
247 EXC( mov.l r0,@r5 )
287 EXC( mov.l @r4+,r0 )
289 EXC( mov.l r0,@r5 )
305 EXC( mov.w @r4+,r0 )
306 EXC( mov.w r0,@r5 )
315 EXC( mov.b @r4+,r0 )
[all …]
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| /arch/alpha/kernel/ |
| A D | traps.c | 401 EXC(1b,3b,%1,%0) in do_entUna()
402 EXC(2b,3b,%2,%0) in do_entUna()
417 EXC(1b,3b,%1,%0) in do_entUna()
418 EXC(2b,3b,%2,%0) in do_entUna()
433 EXC(1b,3b,%1,%0) in do_entUna()
434 EXC(2b,3b,%2,%0) in do_entUna()
458 EXC(1b,5b,%2,%0) in do_entUna()
459 EXC(2b,5b,%1,%0) in do_entUna()
482 EXC(1b,5b,%2,%0) in do_entUna()
483 EXC(2b,5b,%1,%0) in do_entUna()
[all …]
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| /arch/alpha/include/asm/ |
| A D | uaccess.h | 39 #define EXC(label,cont,res,err) \ macro
88 EXC(1b,2b,%0,%1) \
95 EXC(1b,2b,%0,%1) \
102 EXC(1b,2b,%0,%1) \
109 EXC(1b,2b,%0,%1) \
154 EXC(1b,2b,$31,%0) \
161 EXC(1b,2b,$31,%0) \
168 EXC(1b,2b,$31,%0) \
175 EXC(1b,2b,$31,%0) \
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| A D | futex.h | 23 EXC(1b,3b,$31,%1) \
24 EXC(2b,3b,$31,%1) \
84 EXC(1b,3b,$31,%0) in futex_atomic_cmpxchg_inatomic()
85 EXC(2b,3b,$31,%0) in futex_atomic_cmpxchg_inatomic()
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| /arch/mips/lib/ |
| A D | memcpy.S | 115 #define EXC(insn, type, reg, addr, handler) \ macro
149 #define LOAD(reg, addr, handler) EXC(ld, LD_INSN, reg, addr, handler)
150 #define LOADL(reg, addr, handler) EXC(ldl, LD_INSN, reg, addr, handler)
151 #define LOADR(reg, addr, handler) EXC(ldr, LD_INSN, reg, addr, handler)
154 #define STORE(reg, addr, handler) EXC(sd, ST_INSN, reg, addr, handler)
186 #define LOAD(reg, addr, handler) EXC(lw, LD_INSN, reg, addr, handler)
187 #define LOADL(reg, addr, handler) EXC(lwl, LD_INSN, reg, addr, handler)
188 #define LOADR(reg, addr, handler) EXC(lwr, LD_INSN, reg, addr, handler)
191 #define STORE(reg, addr, handler) EXC(sw, ST_INSN, reg, addr, handler)
204 #define LOADB(reg, addr, handler) EXC(lb, LD_INSN, reg, addr, handler)
[all …]
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| A D | csum_partial.S | 346 #define EXC(insn, type, reg, addr) \ macro
372 #define LOAD(reg, addr) EXC(ld, LD_INSN, reg, addr)
374 #define LOADL(reg, addr) EXC(ldl, LD_INSN, reg, addr)
375 #define LOADR(reg, addr) EXC(ldr, LD_INSN, reg, addr)
376 #define STOREB(reg, addr) EXC(sb, ST_INSN, reg, addr)
379 #define STORE(reg, addr) EXC(sd, ST_INSN, reg, addr)
392 #define LOAD(reg, addr) EXC(lw, LD_INSN, reg, addr)
394 #define LOADL(reg, addr) EXC(lwl, LD_INSN, reg, addr)
395 #define LOADR(reg, addr) EXC(lwr, LD_INSN, reg, addr)
396 #define STOREB(reg, addr) EXC(sb, ST_INSN, reg, addr)
[all …]
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| /arch/x86/lib/ |
| A D | checksum_32.S | 263 #define EXC(y...) \ macro
288 EXC(1: movw (%esi), %bx )
290 EXC( movw %bx, (%edi) )
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| /arch/alpha/lib/ |
| A D | csum_partial_copy.c | 49 EXC(1b,2b,%0,%1) \
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| /arch/m68k/ifpsp060/src/ |
| A D | fpsp.S | 16162 # then, the SNAN bit is set in the FPSR EXC byte. If the SNAN trap #
|