Searched refs:FSR (Results 1 – 10 of 10) sorted by relevance
| /arch/arm/include/debug/ |
| A D | renesas-scif.S | 17 #define FSR 0x08 macro
21 #define FSR 0x14 macro
25 #define FSR 0x10 macro
40 1001: ldrh \rd, [\rx, #FSR]
47 ldrh \rd, [\rx, #FSR]
49 strh \rd, [\rx, #FSR]
53 1001: ldrh \rd, [\rx, #FSR]
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| /arch/arm/mm/ |
| A D | abort-ev4.S | 20 mrc p15, 0, r1, c5, c0, 0 @ get FSR
24 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
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| A D | abort-ev4t.S | 21 mrc p15, 0, r1, c5, c0, 0 @ get FSR
25 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
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| A D | abort-ev5t.S | 21 mrc p15, 0, r1, c5, c0, 0 @ get FSR
26 bic r1, r1, #1 << 11 @ clear bits 11 of FSR
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| A D | abort-ev5tj.S | 21 mrc p15, 0, r1, c5, c0, 0 @ get FSR
23 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
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| A D | abort-ev6.S | 22 mrc p15, 0, r1, c5, c0, 0 @ get FSR
35 bic r1, r1, #1 << 11 @ clear bit 11 of FSR
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| A D | abort-nommu.S | 18 mov r0, #0 @ clear r0, r1 (no FSR/FAR)
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| A D | abort-ev7.S | 18 mrc p15, 0, r1, c5, c0, 0 @ get FSR
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| A D | abort-lv4t.S | 21 mrc p15, 0, r1, c5, c0, 0 @ get FSR
23 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
25 mov r0, #0 @ clear r0, r1 (no FSR/FAR)
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| /arch/arm/ |
| A D | Kconfig | 540 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
544 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
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