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/arch/arm64/boot/dts/cavium/
A Dthunder2-99xx.dts19 reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */
20 <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */
/arch/arm64/boot/dts/freescale/
A Dimx8mm-kontron-bl-osm-s.dts128 "ETH_MDC", "ETH_MDIO", "ETH_A_(S)(R)(G)MII_TXD3",
129 "ETH_A_(S)(R)(G)MII_TXD2", "ETH_A_(S)(R)(G)MII_TXD1",
130 "ETH_A_(S)(R)(G)MII_TXD0", "ETH_A_(R)(G)MII_TX_EN(_ER)",
131 "ETH_A_(R)(G)MII_TX_CLK", "ETH_A_(R)(G)MII_RX_DV(_ER)",
132 "ETH_A_(R)(G)MII_RX_CLK", "ETH_A_(S)(R)(G)MII_RXD0",
133 "ETH_A_(S)(R)(G)MII_RXD1", "ETH_A_(R)(G)MII_RXD2",
134 "ETH_A_(R)(G)MII_RXD3";
A Dimx8mm-kontron-osm-s.dtsi186 "ETH_MDC", "ETH_MDIO", "ETH_A_(S)(R)(G)MII_TXD3",
187 "ETH_A_(S)(R)(G)MII_TXD2", "ETH_A_(S)(R)(G)MII_TXD1",
188 "ETH_A_(S)(R)(G)MII_TXD0", "ETH_A_(R)(G)MII_TX_EN(_ER)",
189 "ETH_A_(R)(G)MII_TX_CLK", "ETH_A_(R)(G)MII_RX_DV(_ER)",
190 "ETH_A_(R)(G)MII_RX_CLK", "ETH_A_(S)(R)(G)MII_RXD0",
191 "ETH_A_(S)(R)(G)MII_RXD1", "ETH_A_(R)(G)MII_RXD2",
192 "ETH_A_(R)(G)MII_RXD3";
518 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 /* ETH_A_(R)(G)MII_RXD3 */
519 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 /* ETH_A_(R)(G)MII_RXD2 */
522 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f /* ETH_A_(R)(G)MII_TX_CLK */
[all …]
A Dimx93-kontron-osm-s.dtsi310 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e /* ETH_A_(S)(R)(G)MII_RXD0 */
311 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e /* ETH_A_(S)(R)(G)MII_RXD1 */
312 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e /* ETH_A_(R)(G)MII_RXD2 */
313 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e /* ETH_A_(R)(G)MII_RXD3 */
314 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe /* ETH_A_(R)(G)MII_RX_CLK */
316 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e /* ETH_A_(S)(R)(G)MII_TXD0 */
317 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e /* ETH_A_(S)(R)(G)MII_TXD1 */
318 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e /* ETH_A_(S)(R)(G)MII_TXD2 */
319 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e /* ETH_A_(S)(R)(G)MII_TXD3 */
320 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe /* ETH_A_(R)(G)MII_TX_CLK */
[all …]
A Dimx8mp-kontron-osm-s.dtsi458 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 /* ETH_A_(S)(R)(G)MII_RXD0 */
459 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 /* ETH_A_(S)(R)(G)MII_RXD1 */
460 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 /* ETH_A_(R)(G)MII_RXD2 */
461 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 /* ETH_A_(R)(G)MII_RXD3 */
462 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 /* ETH_A_(R)(G)MII_RX_CLK */
464 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f /* ETH_A_(S)(R)(G)MII_TXD0 */
465 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f /* ETH_A_(S)(R)(G)MII_TXD1 */
466 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f /* ETH_A_(S)(R)(G)MII_TXD2 */
468 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f /* ETH_A_(R)(G)MII_TX_CLK */
479 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 /* ETH_B_(R)(G)MII_RXD2 */
[all …]
/arch/arm64/boot/dts/broadcom/stingray/
A Dstingray-board-base.dtsi23 reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */
24 <0x00000008 0x80000000 0x1 0x80000000>; /* 6G @ 34G */
/arch/arm/boot/dts/st/
A Dstm32mp13-pinctrl.dtsi36 <STM32_PINMUX('G', 9, AF13)>,/* DCMI_VSYNC */
40 <STM32_PINMUX('G', 10, AF13)>,/* DCMI_D2 */
58 <STM32_PINMUX('G', 10, ANALOG)>,/* DCMI_D2 */
77 <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */
98 <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */
128 <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */
167 <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */
188 <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */
218 <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */
334 <STM32_PINMUX('G', 7, AF14)>, /* LCD_R2 */
[all …]
A Dstm32mp15-pinctrl.dtsi520 <STM32_PINMUX('G', 13, AF11)>, /* ETH1_TXD0 */
521 <STM32_PINMUX('G', 14, AF11)>; /* ETH1_TXD1 */
700 <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */
972 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
973 <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
1166 <STM32_PINMUX('G', 13, AF14)>, /* LCD_R0 */
1181 <STM32_PINMUX('G', 8, AF14)>, /* LCD_G7 */
1183 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
1184 <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
1250 <STM32_PINMUX('G', 12, AF14)>, /* LTDC_B1 */
[all …]
A Dstm32mp157c-ultra-fly-sbc.dts446 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
447 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
448 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
483 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
484 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
629 pinmux = <STM32_PINMUX('G', 7, AF9)>; /* QSPI_CLK */
638 pinmux = <STM32_PINMUX('G', 7, ANALOG)>; /* QSPI_CLK */
723 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
753 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
767 <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
[all …]
A Dstm32f7-pinctrl.dtsi279 pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
280 <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
292 pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
293 <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
310 pinmux = <STM32_PINMUX('G', 9, ANALOG)>, /* SDMMC2 D0 */
311 <STM32_PINMUX('G', 10, ANALOG)>, /* SDMMC2 D1 */
404 <STM32_PINMUX('G',12, AF9)>, /* LCD_B4 */
A Dstm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts93 pinmux = <STM32_PINMUX('G', 10, AF14)>, /* LTDC_B2 */
102 <STM32_PINMUX('G', 7, AF14)>, /* LTDC_CLK */
103 <STM32_PINMUX('G', 12, AF14)>, /* LTDC_B1 */
/arch/arm64/boot/dts/renesas/
A Dr9a09g047e57-smarc.dts155 pinmux = <RZG3E_PORT_PINMUX(G, 0, 1)>, /* SD1CLK */
156 <RZG3E_PORT_PINMUX(G, 1, 1)>; /* SD1CMD */
160 pinmux = <RZG3E_PORT_PINMUX(G, 2, 1)>, /* SD1DAT0 */
161 <RZG3E_PORT_PINMUX(G, 3, 1)>, /* SD1DAT1 */
162 <RZG3E_PORT_PINMUX(G, 4, 1)>, /* SD1DAT2 */
163 <RZG3E_PORT_PINMUX(G, 5, 1)>; /* SD1DAT3 */
A Dulcb-kf-audio-graph-card-mix+split.dtsi18 * (G) CPU6 (2ch) <---- (6ch) (Z) PCM3168A-c (TDM-a: 0,1ch)
30 * (G) arecord -D plughw:1,4 xxx.wav (TDM-a)
51 &snd_kf5 /* (G) CPU6 */
110 /* (G) CPU6 <- PCM3168A-c */
187 * (G) CPU6
A Dulcb-kf-audio-graph-card2-mix+split.dtsi18 * (G) CPU6 (2ch) <---- (6ch) (Z) PCM3168A-c (TDM-a: 0,1ch)
30 * (G) arecord -D plughw:1,4 xxx.wav (TDM-a)
51 &fe_g /* (G) CPU6 */
75 * (G) CPU6
194 * (G) CPU6
A Dulcb-kf-simple-audio-card-mix+split.dtsi18 * (G) CPU6 (2ch) <---- (6ch) (Z) PCM3168A-c (TDM-a: 0,1ch)
30 * (G) arecord -D plughw:1,4 xxx.wav (TDM-a)
104 * (G) CPU6
182 * (G) CPU6
/arch/arm/boot/dts/marvell/
A Darmada-xp-crs305-1g-4s.dts3 * Device Tree file for MikroTik CRS305-1G-4S+ board
12 model = "MikroTik CRS305-1G-4S+";
A Darmada-xp-crs326-24g-2s.dts3 * Device Tree file for MikroTik CRS326-24G-2S+ board
12 model = "MikroTik CRS326-24G-2S+";
A Darmada-xp-crs326-24g-2s-bit.dts3 * Device Tree file for MikroTik CRS326-24G-2S+ Bit board
12 model = "MikroTik CRS326-24G-2S+ Bit";
A Darmada-xp-crs305-1g-4s-bit.dts3 * Device Tree file for MikroTik CRS305-1G-4S+ Bit board
12 model = "MikroTik CRS305-1G-4S+ Bit";
/arch/arm64/boot/dts/exynos/
A Dexynos990-x1s.dts3 * Samsung Galaxy S20 5G (x1s/SM-G981B) device tree source
15 model = "Samsung Galaxy S20 5G";
/arch/arm64/boot/dts/nvidia/
A Dtegra194-p3668-0000.dtsi17 cd-gpios = <&gpio TEGRA194_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW>;
28 gpio = <&gpio TEGRA194_MAIN_GPIO(G, 2) GPIO_ACTIVE_HIGH>;
/arch/x86/kernel/
A Didt.c21 #define G(_vector, _addr, _ist, _type, _dpl, _segment) \ macro
34 G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL0, __KERNEL_CS)
38 G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL3, __KERNEL_CS)
46 G(_vector, _addr, _ist + 1, GATE_INTERRUPT, DPL0, __KERNEL_CS)
53 G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3)
/arch/arm/boot/dts/samsung/
A Dexynos4212-tab3-3g8.dts3 * Samsung's Exynos4212 based Galaxy Tab 3 8.0 3G board device tree
14 model = "Samsung Galaxy Tab 3 8.0 3G (SM-T311) based on Exynos4212";
/arch/arm/boot/dts/microchip/
A Dlan966x-kontron-kswitch-d10-mmt-8g.dts3 * Device Tree file for the Kontron KSwitch D10 MMT 8G
10 model = "Kontron KSwitch D10 MMT 8G";
/arch/arm64/boot/dts/marvell/
A Darmada-7040-mochabin.dts33 /* SFP+ 10G */
43 /* SFP 1G */
190 /* mikroBUS, 1G SFP and GPIO expander */
225 /* IS31FL3199, mini-PCIe and 10G SFP+ */
379 /* 10G SFP+ */
402 /* 1G SFP or 1G RJ45 */

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