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Searched refs:GEN_READ_WB_REG_CASES (Results 1 – 3 of 3) sorted by relevance

/arch/loongarch/kernel/
A Dhw_breakpoint.c46 #define GEN_READ_WB_REG_CASES(OFF, REG, T, VAL) \ macro
83 GEN_READ_WB_REG_CASES(CSR_CFG_ADDR, ADDR, t, val); in read_wb_reg()
84 GEN_READ_WB_REG_CASES(CSR_CFG_MASK, MASK, t, val); in read_wb_reg()
85 GEN_READ_WB_REG_CASES(CSR_CFG_CTRL, CTRL, t, val); in read_wb_reg()
86 GEN_READ_WB_REG_CASES(CSR_CFG_ASID, ASID, t, val); in read_wb_reg()
/arch/arm64/kernel/
A Dhw_breakpoint.c71 #define GEN_READ_WB_REG_CASES(OFF, REG, VAL) \ macro
112 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val); in read_wb_reg()
113 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val); in read_wb_reg()
114 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WVR, AARCH64_DBG_REG_NAME_WVR, val); in read_wb_reg()
115 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WCR, AARCH64_DBG_REG_NAME_WCR, val); in read_wb_reg()
/arch/arm/kernel/
A Dhw_breakpoint.c59 #define GEN_READ_WB_REG_CASES(OP2, VAL) \ macro
100 GEN_READ_WB_REG_CASES(ARM_OP2_BVR, val); in read_wb_reg()
101 GEN_READ_WB_REG_CASES(ARM_OP2_BCR, val); in read_wb_reg()
102 GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val); in read_wb_reg()
103 GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val); in read_wb_reg()

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