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/arch/arm/boot/dts/aspeed/
A Daspeed-bmc-nvidia-gb200nvl-bmc.dts297 "M2_1_PRSNT_L-I","",
298 "M2_0_PRSNT_L-I","",
316 "FAN_FAIL_IN_L-I","",
326 "PCIE_WAKE_L-I","",
330 "UID_BTN_N-I","",
331 "PWR_BTN_L-I","",
345 "DP_HPD-I","",
446 "PS_RUN_IO0_PG-I",
562 "MCU_GPIO-I",
924 "HMC_PRSNT_L-I",
[all …]
/arch/powerpc/perf/
A Dhv-gpci-requests.h51 #include I(REQUEST_BEGIN)
67 #include I(REQUEST_END)
72 #include I(REQUEST_BEGIN)
80 #include I(REQUEST_END)
95 #include I(REQUEST_END)
106 #include I(REQUEST_END)
121 #include I(REQUEST_END)
136 #include I(REQUEST_END)
165 #include I(REQUEST_END)
182 #include I(REQUEST_END)
[all …]
/arch/loongarch/include/asm/
A Datomic.h37 #define ATOMIC_OP(op, I, asm_op) \ argument
43 : "r" (I) \
55 : "r" (I) \
58 return result c_op I; \
69 : "r" (I) \
76 ATOMIC_OP(op, I, asm_op) \
105 ATOMIC_OP(op, I, asm_op) \
203 : "r" (I) \
214 : "r" (I) \
217 return result c_op I; \
[all …]
/arch/xtensa/variants/test_kc705_hifi/include/variant/
A Dtie-asm.h222 AE_S64.I aed0, \ptr, .Lxchal_ofs_+24
223 AE_S64.I aed1, \ptr, .Lxchal_ofs_+32
224 AE_S64.I aed2, \ptr, .Lxchal_ofs_+40
225 AE_S64.I aed3, \ptr, .Lxchal_ofs_+48
226 AE_S64.I aed4, \ptr, .Lxchal_ofs_+56
228 AE_S64.I aed5, \ptr, .Lxchal_ofs_+0
229 AE_S64.I aed6, \ptr, .Lxchal_ofs_+8
230 AE_S64.I aed7, \ptr, .Lxchal_ofs_+16
231 AE_S64.I aed8, \ptr, .Lxchal_ofs_+24
285 AE_L64.I aed5, \ptr, .Lxchal_ofs_+0
[all …]
/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
A Dtie-asm.h116 AE_SP24X2S.I aep6, \ptr, 0
117 AE_SP24X2S.I aep7, \ptr, 8
118 AE_SQ56S.I aeq0, \ptr, 16
119 AE_SQ56S.I aeq1, \ptr, 24
120 AE_SQ56S.I aeq2, \ptr, 32
121 AE_SQ56S.I aeq3, \ptr, 40
146 AE_LQ56.I aeq0, \ptr, 0
147 AE_LQ56.I aeq1, \ptr, 8
148 AE_LQ56.I aeq2, \ptr, 16
149 AE_LQ56.I aeq3, \ptr, 24
[all …]
/arch/riscv/include/asm/
A Datomic.h60 : "r" (I) \
65 #define ATOMIC_OPS(op, asm_op, I) \ argument
66 ATOMIC_OP (op, asm_op, I, w, int, )
68 #define ATOMIC_OPS(op, asm_op, I) \ argument
70 ATOMIC_OP (op, asm_op, I, d, s64, 64)
96 : "r" (I) \ in ATOMIC_OPS()
107 : "r" (I) \
126 #define ATOMIC_OPS(op, asm_op, c_op, I) \ argument
130 #define ATOMIC_OPS(op, asm_op, c_op, I) \
165 #define ATOMIC_OPS(op, asm_op, I) \ argument
[all …]
/arch/mips/ralink/
A DPlatform4 cflags-$(CONFIG_RALINK) += -I$(srctree)/arch/mips/include/asm/mach-ralink
10 cflags-$(CONFIG_SOC_RT288X) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt288x
16 cflags-$(CONFIG_SOC_RT305X) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt305x
22 cflags-$(CONFIG_SOC_RT3883) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt3883
28 cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
33 cflags-$(CONFIG_SOC_MT7621) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
/arch/arm/boot/dts/nxp/vf/
A Dvf610-zii-dev-rev-c.dts298 * I/O0 - ENET_SWR_EN
299 * I/O1 - ESW1_RESETn
300 * I/O2 - ARINC_RESET
302 * I/O4 - ESW2_RESETn
303 * I/O5 - ESW3_RESETn
304 * I/O6 - ESW4_RESETn
305 * I/O8 - TP909
306 * I/O9 - FEM_SEL
308 * I/O11 - PHY_RSTn
309 * I/O12 - OPT1_SD
[all …]
/arch/mips/lantiq/
A DPlatform5 cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq
7 cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway
8 cflags-$(CONFIG_SOC_FALCON) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon
/arch/arm/boot/dts/st/
A Dstm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts112 <STM32_PINMUX('I', 0, AF14)>, /* LTDC_G5 */
113 <STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */
114 <STM32_PINMUX('I', 2, AF14)>, /* LTDC_G7 */
115 <STM32_PINMUX('I', 4, AF14)>, /* LTDC_B4 */
116 <STM32_PINMUX('I', 5, AF14)>, /* LTDC_B5 */
118 <STM32_PINMUX('I', 7, AF14)>, /* LTDC_B7 */
119 <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */
120 <STM32_PINMUX('I', 10, AF14)>; /* LTDC_HSYNC */
A Dstm32mp15-pinctrl.dtsi120 <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
123 <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
125 <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
142 <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
145 <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
147 <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
198 <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
199 <STM32_PINMUX('I', 6, AF13)>,/* DCMI_D6 */
201 <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
218 <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
[all …]
/arch/arm/mm/
A Dproc-arm926.S72 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
75 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
99 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
113 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
141 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
164 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
167 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
213 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
238 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
371 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
[all …]
A Dcache-v4wt.S49 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
71 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
93 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
128 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
147 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache
A Dproc-arm925.S112 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
115 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
134 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
147 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
178 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
201 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
204 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
208 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
250 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
275 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
A Dproc-mohawk.S65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
67 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
96 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
119 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
143 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
146 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
186 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
211 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
324 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
386 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches
[all …]
A Dproc-arm920.S80 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
83 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
111 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
140 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
163 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
201 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
226 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
357 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
360 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
396 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
[all …]
A Dproc-arm922.S82 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
85 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
113 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
142 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
165 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
203 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
228 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
360 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
363 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
387 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
[all …]
A Dcache-v6.S43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
46 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
52 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
69 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
152 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
A Dproc-arm1022.S88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
155 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
185 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
225 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
388 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
392 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
417 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
420 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
A Dproc-arm1026.S88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
150 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
180 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
220 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
378 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
382 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
407 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
410 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
A Dproc-xscale.S150 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB
151 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
163 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
195 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
241 mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
273 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
291 mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry
318 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
457 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
529 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
[all …]
A Dproc-arm946.S63 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
90 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
120 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
148 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
152 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
155 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
195 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
221 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
337 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
A Dproc-arm1020e.S88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
156 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
186 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
226 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
396 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
400 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
425 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
428 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
/arch/mips/sibyte/
A DPlatform9 -I$(srctree)/arch/mips/include/asm/mach-sibyte \
13 -I$(srctree)/arch/mips/include/asm/mach-sibyte \
17 -I$(srctree)/arch/mips/include/asm/mach-sibyte \
/arch/arm/boot/dts/nxp/imx/
A Dimx6qdl-dhcom-picoitx.dtsi20 gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
38 "DHCOM-I", "PicoITX-HW2", "", "", "", "", "", "",
56 * I: yellow led

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