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Searched refs:ICH_VMCR_ENG0_MASK (Results 1 – 4 of 4) sorted by relevance

/arch/arm64/kvm/vgic/
A Dvgic-v3-nested.c202 if ((hcr & ICH_HCR_EL2_VGrp0EIE) && (vmcr & ICH_VMCR_ENG0_MASK)) in vgic_v3_get_misr()
205 if ((hcr & ICH_HCR_EL2_VGrp0DIE) && !(vmcr & ICH_VMCR_ENG0_MASK)) in vgic_v3_get_misr()
A Dvgic-v3.c219 vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK; in vgic_v3_set_vmcr()
252 vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT; in vgic_v3_get_vmcr()
/arch/arm64/kvm/hyp/
A Dvgic-v3-sr.c570 if (!(val & ICH_LR_GROUP) && !(vmcr & ICH_VMCR_ENG0_MASK)) in __vgic_v3_highest_priority_lr()
860 vcpu_set_reg(vcpu, rt, !!(vmcr & ICH_VMCR_ENG0_MASK)); in __vgic_v3_read_igrpen0()
873 vmcr |= ICH_VMCR_ENG0_MASK; in __vgic_v3_write_igrpen0()
875 vmcr &= ~ICH_VMCR_ENG0_MASK; in __vgic_v3_write_igrpen0()
/arch/arm64/include/asm/
A Dsysreg.h1018 #define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT) macro

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