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Searched refs:IDENT_ADDR (Results 1 – 20 of 20) sorted by relevance

/arch/alpha/include/asm/
A Dcore_cia.h109 #define CIA_IOC_CFG (IDENT_ADDR + 0x8740000480UL)
217 (IDENT_ADDR + 0x8760000800UL + (n)*0x40)
227 #define CIA_CONF (IDENT_ADDR + 0x8700000000UL)
228 #define CIA_IO (IDENT_ADDR + 0x8580000000UL)
234 #define CIA_BW_IO (IDENT_ADDR + 0x8900000000UL)
248 #define GRU_SCR (IDENT_ADDR + 0x8780000300UL)
249 #define GRU_LED (IDENT_ADDR + 0x8780000800UL)
250 #define GRU_RESET (IDENT_ADDR + 0x8780000900UL)
263 #define PYXIS_GPO (IDENT_ADDR + 0x87A0000180UL)
452 return addr >= IDENT_ADDR + 0x8000000000UL; in cia_is_ioaddr()
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A Dcore_t2.h35 #define T2_IO (IDENT_ADDR + GAMMA_BIAS + 0x3a0000000UL)
39 #define T2_IOCSR (IDENT_ADDR + GAMMA_BIAS + 0x38e000000UL)
40 #define T2_CERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000020UL)
41 #define T2_CERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000040UL)
42 #define T2_CERR3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000060UL)
43 #define T2_PERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000080UL)
44 #define T2_PERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000a0UL)
45 #define T2_PSCR (IDENT_ADDR + GAMMA_BIAS + 0x38e0000c0UL)
46 #define T2_HAE_1 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000e0UL)
47 #define T2_HAE_2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000100UL)
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A Dcore_polaris.h22 #define POLARIS_SPARSE_MEM_BASE (IDENT_ADDR + 0xf800000000UL)
23 #define POLARIS_DENSE_MEM_BASE (IDENT_ADDR + 0xf900000000UL)
24 #define POLARIS_SPARSE_IO_BASE (IDENT_ADDR + 0xf980000000UL)
25 #define POLARIS_SPARSE_CONFIG_BASE (IDENT_ADDR + 0xf9c0000000UL)
26 #define POLARIS_IACK_BASE (IDENT_ADDR + 0xf9f8000000UL)
27 #define POLARIS_DENSE_IO_BASE (IDENT_ADDR + 0xf9fc000000UL)
28 #define POLARIS_DENSE_CONFIG_BASE (IDENT_ADDR + 0xf9fe000000UL)
A Dcore_mcpcia.h89 #define MCPCIA_SPARSE(m) (IDENT_ADDR + 0xf000000000UL + MCPCIA_MID(m))
90 #define MCPCIA_DENSE(m) (IDENT_ADDR + 0xf100000000UL + MCPCIA_MID(m))
91 #define MCPCIA_IO(m) (IDENT_ADDR + 0xf180000000UL + MCPCIA_MID(m))
92 #define MCPCIA_CONF(m) (IDENT_ADDR + 0xf1c0000000UL + MCPCIA_MID(m))
93 #define MCPCIA_CSR(m) (IDENT_ADDR + 0xf1e0000000UL + MCPCIA_MID(m))
94 #define MCPCIA_IO_IACK(m) (IDENT_ADDR + 0xf1f0000000UL + MCPCIA_MID(m))
95 #define MCPCIA_DENSE_IO(m) (IDENT_ADDR + 0xe1fc000000UL + MCPCIA_MID(m))
96 #define MCPCIA_DENSE_CONF(m) (IDENT_ADDR + 0xe1fe000000UL + MCPCIA_MID(m))
A Dcore_irongate.h124 #define IRONGATE_MEM (IDENT_ADDR | IRONGATE_BIAS | 0x000000000UL)
125 #define IRONGATE_IACK_SC (IDENT_ADDR | IRONGATE_BIAS | 0x1F8000000UL)
126 #define IRONGATE_IO (IDENT_ADDR | IRONGATE_BIAS | 0x1FC000000UL)
127 #define IRONGATE_CONF (IDENT_ADDR | IRONGATE_BIAS | 0x1FE000000UL)
A Dcore_tsunami.h89 #define TSUNAMI_cchip ((tsunami_cchip *)(IDENT_ADDR+TS_BIAS+0x1A0000000UL))
90 #define TSUNAMI_dchip ((tsunami_dchip *)(IDENT_ADDR+TS_BIAS+0x1B0000800UL))
91 #define TSUNAMI_pchip0 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x180000000UL))
92 #define TSUNAMI_pchip1 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x380000000UL))
257 #define TSUNAMI_BASE (IDENT_ADDR + TS_BIAS)
A Dcore_titan.h127 #define TITAN_cchip ((titan_cchip *)(IDENT_ADDR+TI_BIAS+0x1A0000000UL))
128 #define TITAN_dchip ((titan_dchip *)(IDENT_ADDR+TI_BIAS+0x1B0000800UL))
129 #define TITAN_pachip0 ((titan_pachip *)(IDENT_ADDR+TI_BIAS+0x180000000UL))
130 #define TITAN_pachip1 ((titan_pachip *)(IDENT_ADDR+TI_BIAS+0x380000000UL))
299 #define TITAN_BASE (IDENT_ADDR + TI_BIAS)
A Dmmu_context.h203 = ((unsigned long)mm->pgd - IDENT_ADDR) >> PAGE_SHIFT; in init_new_context()
212 = ((unsigned long)mm->pgd - IDENT_ADDR) >> PAGE_SHIFT; in enter_lazy_tlb()
A Dio.h17 #define IDENT_ADDR 0xffff800000000000UL macro
19 #define IDENT_ADDR 0xfffffc0000000000UL macro
57 return (unsigned long)address - IDENT_ADDR; in virt_to_phys()
62 return (void *) (address + IDENT_ADDR); in phys_to_virt()
81 return (void *)(IDENT_ADDR + (address & ((1ul << 41) - 1))); in phys_to_virt()
A Ddma.h120 ~0UL : IDENT_ADDR + 0x01000000)
A Dcore_wildfire.h223 #define WILDFIRE_BASE (IDENT_ADDR | (1UL << 40))
A Dcore_marvel.h54 #define EV7_KERN_ADDR(addr) ((void *)(IDENT_ADDR | EV7_MASK40(addr)))
/arch/alpha/kernel/
A Dcore_polaris.c169 hose->dense_mem_base = POLARIS_DENSE_MEM_BASE - IDENT_ADDR; in polaris_init_arch()
171 hose->dense_io_base = POLARIS_DENSE_IO_BASE - IDENT_ADDR; in polaris_init_arch()
A Dcore_t2.c446 hose->sparse_mem_base = T2_SPARSE_MEM - IDENT_ADDR; in t2_init_arch()
447 hose->dense_mem_base = T2_DENSE_MEM - IDENT_ADDR; in t2_init_arch()
448 hose->sparse_io_base = T2_IO - IDENT_ADDR; in t2_init_arch()
A Dcore_cia.c701 hose->sparse_mem_base = CIA_SPARSE_MEM - IDENT_ADDR; in do_init_arch()
702 hose->dense_mem_base = CIA_DENSE_MEM - IDENT_ADDR; in do_init_arch()
703 hose->sparse_io_base = CIA_IO - IDENT_ADDR; in do_init_arch()
707 hose->dense_mem_base = CIA_BW_MEM - IDENT_ADDR; in do_init_arch()
709 hose->dense_io_base = CIA_BW_IO - IDENT_ADDR; in do_init_arch()
A Dcore_mcpcia.c304 hose->sparse_mem_base = MCPCIA_SPARSE(mid) - IDENT_ADDR; in mcpcia_new_hose()
305 hose->dense_mem_base = MCPCIA_DENSE(mid) - IDENT_ADDR; in mcpcia_new_hose()
306 hose->sparse_io_base = MCPCIA_IO(mid) - IDENT_ADDR; in mcpcia_new_hose()
A Derr_common.c245 (IDENT_ADDR | pcpu->console_data_log_pa); in cdl_process_console_data_log()
A Dcore_marvel.c716 addr = IDENT_ADDR | (baddr - __direct_map_base); in marvel_ioremap()
A Dpci_iommu.c813 if (!__direct_map_base && MAX_DMA_ADDRESS - IDENT_ADDR - 1 <= mask) in alpha_pci_supported()
/arch/alpha/mm/
A Dfault.c52 pcb->ptbr = ((unsigned long) next_mm->pgd - IDENT_ADDR) >> PAGE_SHIFT; in __load_new_mm_context()

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