Searched refs:INTC (Results 1 – 8 of 8) sorted by relevance
| /arch/mips/pci/ |
| A D | fixup-sni.c | 26 #define INTC PCIMT_IRQ_INTC macro
50 { 0, INTB, INTC, INTD, INTA }, /* Slot 2 */
51 { 0, INTC, INTD, INTA, INTB }, /* Slot 3 */
52 { 0, INTD, INTA, INTB, INTC }, /* Slot 4 */
64 { 0, INTC, INTD, INTA, INTB }, /* Slot 1 */
67 { 0, INTB, INTC, INTD, INTA }, /* Slot 2 */
68 { 0, INTC, INTD, INTA, INTB }, /* Slot 3 */
69 { 0, INTD, INTA, INTB, INTC }, /* Slot 4 */
77 { 0, INTD, INTA, INTB, INTC }, /* Slot 1 */
84 #undef INTC
[all …]
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| A D | fixup-ip32.c | 23 #define INTC MACEPCI_SHARED1_IRQ macro
30 {0, INTA0, INTB, INTC, INTD},
31 {0, INTA1, INTC, INTD, INTB},
32 {0, INTA2, INTD, INTB, INTC},
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| /arch/arc/boot/dts/ |
| A D | axc001.dtsi | 83 * This INTC is actually connected to DW APB GPIO
84 * which acts as a wire between MB INTC and CPU INTC.
85 * GPIO INTC is configured in platform init code
86 * and here we mimic direct connection from MB INTC to
87 * CPU INTC, thus we set "interrupts = <7>" instead of
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| A D | axc003_idu.dtsi | 127 * This INTC is actually connected to DW APB GPIO
128 * which acts as a wire between MB INTC and CPU INTC.
129 * GPIO INTC is configured in platform init code
130 * and here we mimic direct connection from MB INTC to
131 * CPU INTC, thus we set "interrupts = <0 1>" instead of
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| /arch/powerpc/boot/dts/ |
| A D | holly.dts | 157 | The INTA, INTB, INTC, INTD are shared.
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| A D | katmai.dts | 309 * INTC: J2: 1-2
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| /arch/arm64/boot/dts/socionext/ |
| A D | uniphier-ld20.dtsi | 943 <0 0 0 3 &pcie_intc 2>, /* INTC */
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| A D | uniphier-pxs3.dtsi | 917 <0 0 0 3 &pcie_intc 2>, /* INTC */
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