| /arch/alpha/lib/ |
| A D | ev67-strncat.S | 58 bsr $23, __stxncpy # L0 :/* Now do the append. */
65 ret # L0 :
81 ret # L0 :
87 ret # L0 :
93 ret # L0 :
|
| A D | ev6-divide.S | 208 ret $31,($23),1 # L0 : L U U L
246 bsr $23,ufunction # L0: L U L U
261 ret $31,($23),1 # L0 : L U U L
|
| A D | ev6-memset.S | 214 ret $31,($26),1 # L0 :
231 ret $31,($26),1 # L0 :
392 ret $31,($26),1 # L0 :
409 ret $31,($26),1 # L0 :
580 ret $31,($26),1 # L0 :
597 ret $31,($26),1 # L0 :
|
| A D | ev67-strlen.S | 48 ret $31, ($26) # L0 :
|
| A D | ev6-memchr.S | 96 ret # L0 : L U L U
120 ret # L0 : L U L U
190 ret # L0 :
|
| A D | ev67-strcat.S | 53 br __stxcpy # L0 :
|
| A D | ev6-memcpy.S | 87 ldq $6, 0($17) # L0 : bytes 0..7
176 ret $31, ($26), 1 # L0 :
240 ret $31, ($26), 1 # L0 :
|
| A D | ev6-stxncpy.S | 133 ret (t9) # L0 : Latency=3
140 br $a_eos # L0 : Latency=3
312 ret (t9) # L0 : Latency=3
333 br $u_final # L0 : Latency=3
393 ret (t9) # L0 : Latency=3
|
| A D | ev6-copy_user.S | 119 br $31, $dirtyentry # L0 .. .. .. : L U U L
224 ret $31,($26),1 # L0 .. .. .. : L U L U
|
| A D | ev6-stxcpy.S | 109 ret (t9) # L0 : Latency=3
135 br stxcpy_aligned # L0 : Latency=3
259 ret (t9) # L0 : Latency=3
|
| A D | ev67-strchr.S | 87 ret # L0 :
|
| A D | ev6-csum_ipv6_magic.S | 150 ret # L0 : L U L U
|
| A D | ev67-strrchr.S | 106 ret # L0 : Latency=3
|
| A D | ev6-clear_user.S | 211 ret $31, ($26), 1 # L0 .. .. .. : L U L U
|
| /arch/xtensa/lib/ |
| A D | memset.S | 47 .L0: # return here from .Ldstunaligned when dst is aligned label
113 bbci.l a5, 1, .L0 # if now aligned, return to main algorithm
120 j .L0 # dst is now aligned, return to main algorithm
|
| /arch/sparc/net/ |
| A D | bpf_jit_64.h | 20 #define L0 0x10 macro
|
| /arch/sh/lib/ |
| A D | __clear_user.S | 36 .L0: dt r3 define
38 bf/s .L0
|
| /arch/powerpc/kvm/ |
| A D | Kconfig | 161 bool "Nested L0 host workaround for L1 KVM host PMU handling bug" if EXPERT
166 reflect the PMU in-use status of their L2 guest to the L0 host
171 Selecting this option for the L0 host implements a workaround for
182 L0-Hypervisor stats on a kvm-hv enabled PSeries LPAR like:
|
| /arch/arm/mach-omap2/ |
| A D | sram242x.S | 62 mov r9, #0x0 @ shift back to L0-voltage
67 str r3, [r2] @ go to L0-freq operation
101 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
196 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
|
| A D | sram243x.S | 62 mov r9, #0x0 @ shift back to L0-voltage
67 str r3, [r2] @ go to L0-freq operation
101 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
196 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
|
| /arch/arm/boot/dts/aspeed/ |
| A D | aspeed-bmc-qcom-dc-scm-v1.dts | 106 /*L0-L7*/ "","","","","","","","",
|
| A D | aspeed-bmc-vegman-n110.dts | 26 /*L0-L7*/ "","","","","","","","",
|
| A D | aspeed-bmc-vegman-sx20.dts | 26 /*L0-L7*/ "","","","","","","","",
|
| A D | aspeed-bmc-amd-daytonax.dts | 137 /*L0-L7*/ "","","","","","","","",
|
| A D | aspeed-bmc-inventec-transformers.dts | 282 /*L0-L7*/ "","","","","","","","",
|