| /arch/arc/kernel/ |
| A D | entry-compact.S | 152 ; if L2 IRQ interrupted a L1 ISR, disable preemption
154 ; This is to avoid a potential L1-L2-L1 scenario
155 ; -L1 IRQ taken
156 ; -L2 interrupts L1 (before L1 ISR could run)
160 ; But both L1 and L2 re-enabled, so another L1 can be taken
161 ; while prev L1 is still unserviced
165 ; L2 interrupting L1 implies both L2 and L1 active
167 ; need to check STATUS32_L2 to determine if L1 was active
320 ; use the same priority as rtie: EXCPN, L2 IRQ, L1 IRQ, None
343 ; if L2 IRQ interrupted an L1 ISR, we'd disabled preemption earlier
[all …]
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| /arch/arm/mm/ |
| A D | proc-xsc3.S | 69 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
200 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
201 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
233 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
238 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
280 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
282 mcrne p15, 0, r1, c7, c10, 1 @ clean L1 D line
283 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D line
300 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
[all …]
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| /arch/powerpc/perf/ |
| A D | power8-pmu.c | 133 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
134 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
136 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);
137 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
138 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
139 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
140 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
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| A D | power9-pmu.c | 177 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1_FIN);
178 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
179 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);
180 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
181 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
182 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
183 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
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| A D | power10-pmu.c | 133 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
134 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
135 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_LD_PREFETCH_CACHE_LINE_MISS);
136 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
137 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
138 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
139 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_REQ);
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| A D | generic-compat-pmu.c | 109 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
110 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
111 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
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| /arch/hexagon/lib/ |
| A D | memset.S | 159 if (r2==#0) jump:nt .L1
186 if (p1) jump .L1
197 if (p0.new) jump:nt .L1
208 if (p0.new) jump:nt .L1
284 .L1: label
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| /arch/m68k/lib/ |
| A D | divsi3.S | 95 jpl L1
102 L1: movel sp@(8), d0 /* d0 = dividend */ label
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| A D | udivsi3.S | 144 L1: addl d0,d0 | shift reg pair (p,a) one bit left label
152 jcc L1
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| /arch/alpha/boot/ |
| A D | bootp.c | 65 #define L1 ((unsigned long *) 0x200802000) macro
77 pcb_va->ptbr = L1[1] >> 32; in pal_init()
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| A D | main.c | 59 #define L1 ((unsigned long *) 0x200802000) macro
71 pcb_va->ptbr = L1[1] >> 32; in pal_init()
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| A D | bootpz.c | 113 #define L1 ((unsigned long *) 0x200802000) macro
125 pcb_va->ptbr = L1[1] >> 32; in pal_init()
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| /arch/m68k/fpsp040/ |
| A D | setox.S | 104 | 3.1 R := X + N*L1, where L1 := single-precision(-log2/64).
106 | Notes: a) The way L1 and L2 are chosen ensures L1+L2 approximate
108 | b) N*L1 is exact because N is no longer than 22 bits and
109 | L1 is no longer than 24 bits.
111 | Thus, R is practically X+N(L1+L2) to full 64 bits.
505 fmuls #0xBC317218,%fp0 | ...N * L1, L1 = lead(-log2/64)
506 fmulx L2,%fp2 | ...N * L2, L1+L2 = -log2/64
507 faddx %fp1,%fp0 | ...X + N*L1
671 fmuls #0xBC317218,%fp0 | ...N * L1, L1 = lead(-log2/64)
672 fmulx L2,%fp2 | ...N * L2, L1+L2 = -log2/64
[all …]
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| /arch/riscv/lib/ |
| A D | tishift.S | 10 beqz a2, .L1
21 .L1: label
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| /arch/sparc/net/ |
| A D | bpf_jit_64.h | 21 #define L1 0x11 macro
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| /arch/arm/mach-omap2/ |
| A D | sram242x.S | 39 str r3, [r2] @ go to L1-freq operation
42 mov r9, #0x1 @ set up for L1 voltage call
101 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
105 str r5, [r4] @ Force transition to L1
196 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
200 str r8, [r10] @ Force transition to L1
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| A D | sram243x.S | 39 str r3, [r2] @ go to L1-freq operation
42 mov r9, #0x1 @ set up for L1 voltage call
101 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
105 str r5, [r4] @ Force transition to L1
196 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
200 str r8, [r10] @ Force transition to L1
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| /arch/powerpc/boot/dts/ |
| A D | amigaone.dts | 27 d-cache-size = <32768>; // L1, 32K
28 i-cache-size = <32768>; // L1, 32K
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| A D | mpc866ads.dts | 26 d-cache-size = <0x2000>; // L1, 8K
27 i-cache-size = <0x4000>; // L1, 16K
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| A D | tqm5200.dts | 27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
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| A D | tqm8xx.dts | 33 d-cache-size = <0x1000>; // L1, 4K
34 i-cache-size = <0x1000>; // L1, 4K
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| A D | charon.dts | 30 d-cache-size = <0x4000>; // L1, 16K
31 i-cache-size = <0x4000>; // L1, 16K
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| A D | lite5200.dts | 27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
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| /arch/x86/lib/ |
| A D | csum-copy_64.S | 163 .L1: /* .Lshort rejoins the common path here */ label
207 jmp .L1
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| /arch/arm/boot/dts/broadcom/ |
| A D | bcm2836.dtsi | 44 * https://developer.arm.com/documentation/ddi0464/f/L1-Memory-System
45 * /About-the-L1-memory-system?lang=en
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