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Searched refs:L2 (Results 1 – 25 of 192) sorted by relevance

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/arch/mips/cavium-octeon/
A DKconfig31 bool "Lock often used kernel code in the L2"
34 Enable locking parts of the kernel into the L2 cache.
37 bool "Lock the TLB handler in L2"
41 Lock the low level TLB fast path into L2.
44 bool "Lock the exception handler in L2"
48 Lock the low level exception handler into L2.
51 bool "Lock the interrupt handler in L2"
55 Lock the low level interrupt handler into L2.
58 bool "Lock the 2nd level interrupt handler in L2"
62 Lock the 2nd level interrupt handler in L2.
[all …]
/arch/arc/kernel/
A Dentry-compact.S152 ; if L2 IRQ interrupted a L1 ISR, disable preemption
154 ; This is to avoid a potential L1-L2-L1 scenario
156 ; -L2 interrupts L1 (before L1 ISR could run)
159 ; Returns from L2 context fine
160 ; But both L1 and L2 re-enabled, so another L1 can be taken
165 ; L2 interrupting L1 implies both L2 and L1 active
320 ; use the same priority as rtie: EXCPN, L2 IRQ, L1 IRQ, None
335 ; However the context returning might not have taken L2 intr itself
337 ; Special considerations needed for the context which took L2 intr
339 ld r9, [sp, PT_event] ; Ensure this is L2 intr context
[all …]
/arch/arm/boot/dts/calxeda/
A Dhighbank.dts25 next-level-cache = <&L2>;
44 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
82 next-level-cache = <&L2>;
135 L2: cache-controller { label
/arch/arm/boot/dts/nxp/vf/
A Dvf610.dtsi8 next-level-cache = <&L2>;
12 L2: cache-controller@40006000 { label
/arch/arm/boot/dts/arm/
A Darm-realview-eb-a9mp.dts42 next-level-cache = <&L2>;
49 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
A Dvexpress-v2p-ca9.dts44 next-level-cache = <&L2>;
51 next-level-cache = <&L2>;
58 next-level-cache = <&L2>;
65 next-level-cache = <&L2>;
166 L2: cache-controller@1e00a000 { label
227 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
272 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
286 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
A Darm-realview-eb-11mp.dts46 next-level-cache = <&L2>;
53 next-level-cache = <&L2>;
60 next-level-cache = <&L2>;
67 next-level-cache = <&L2>;
A Dvexpress-v2p-ca5s.dts42 next-level-cache = <&L2>;
49 next-level-cache = <&L2>;
130 L2: cache-controller@2c0f0000 { label
/arch/arm/boot/dts/broadcom/
A Dbcm4708.dtsi31 next-level-cache = <&L2>;
38 next-level-cache = <&L2>;
A Dbcm47081.dtsi29 next-level-cache = <&L2>;
/arch/powerpc/boot/dts/fsl/
A Dmpc8572ds_camp_core1.dts5 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
58 cache-size = <0x80000>; // L2, 512K
80 18 16 10 42 45 58 /* MEM L2 mdio serial crypto */
A Dmpc8572ds_camp_core0.dts5 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
41 cache-size = <0x80000>; // L2, 512K
A Dp1020rdb-pc_camp_core1.dts5 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
102 16 /* ecm, mem, L2, pci0, pci1 */
A Dmpc8572si-pre.dtsi64 next-level-cache = <&L2>;
70 next-level-cache = <&L2>;
A Dp1020si-pre.dtsi62 next-level-cache = <&L2>;
68 next-level-cache = <&L2>;
/arch/powerpc/perf/
A Disa207-common.c226 ret = PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT); in isa207_find_source()
260 ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT); in isa207_find_source()
262 ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HITM); in isa207_find_source()
269 ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HIT) | P(HOPS, 0); in isa207_find_source()
271 ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HITM) | P(HOPS, 0); in isa207_find_source()
/arch/m68k/lib/
A Ddivsi3.S103 jpl L2
111 L2: movel d1, sp@- label
/arch/alpha/kernel/
A Dsetup.c1196 int L1I, L1D, L2, L3; in determine_cpu_caches() local
1219 L2 = external_cache_probe(128*1024, 5); in determine_cpu_caches()
1233 L2 = (car & 1 ? CSHAPE (size, 3, 1) : -1); in determine_cpu_caches()
1247 L2 = CSHAPE (96*1024, width, 3); in determine_cpu_caches()
1281 L2 = ((cbox_config >> 31) & 1 ? CSHAPE (size, 6, 1) : -1); in determine_cpu_caches()
1283 L2 = external_cache_probe(512*1024, 6); in determine_cpu_caches()
1295 L2 = external_cache_probe(1024*1024, 6); in determine_cpu_caches()
1302 L2 = CSHAPE(7*1024*1024/4, 6, 7); in determine_cpu_caches()
1308 L1I = L1D = L2 = L3 = 0; in determine_cpu_caches()
1314 alpha_l2_cacheshape = L2; in determine_cpu_caches()
/arch/riscv/lib/
A Dtishift.S14 blez a5, .L2
23 .L2: label
/arch/arm/mach-omap2/
A DKconfig191 bool "OMAP3 HS/EMU save and restore for L2 AUX control register"
194 Without this option, L2 Auxiliary control register contents are
200 int "Service ID for the support routine to set L2 AUX control"
204 PPA routine service ID for setting L2 auxiliary control register.
266 A livelock can occur in the L2 cache arbitration that might prevent
A Dsleep44xx.S148 ldreq r0, [r8, #L2X0_SAVE_OFFSET0] @ Retrieve L2 state from SAR
310 ldr r12, =OMAP4_MON_L2X0_PREFETCH_INDEX @ Setup L2 PREFETCH
315 ldr r12, =OMAP4_MON_L2X0_AUXCTRL_INDEX @ Setup L2 AUXCTRL
318 ldr r12, =OMAP4_MON_L2X0_CTRL_INDEX @ Enable L2 cache
/arch/sparc/net/
A Dbpf_jit_64.h22 #define L2 0x12 macro
/arch/m68k/fpsp040/
A Dsetox.S105 | 3.2 R := R + N*L2, L2 := extended-precision(-log2/64 - L1).
106 | Notes: a) The way L1 and L2 are chosen ensures L1+L2 approximate
111 | Thus, R is practically X+N(L1+L2) to full 64 bits.
498 movew L2,L_SCR1(%a6) | ...prefetch L2, no need in CB
506 fmulx L2,%fp2 | ...N * L2, L1+L2 = -log2/64
665 | MOVE.W #$3FDC,L2 ...prefetch L2 in CB mode
672 fmulx L2,%fp2 | ...N * L2, L1+L2 = -log2/64
/arch/sh/lib/
A D__clear_user.S82 .L2: dt r3 define
84 bf/s .L2
/arch/arm/boot/dts/hpe/
A Dhpe-gxp.dtsi21 next-level-cache = <&L2>;
48 L2: cache-controller@b0040000 { label

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