| /arch/x86/events/intel/ |
| A D | ds.c | 95 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
97 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
112 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in intel_pmu_pebs_data_source_nhm()
113 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in intel_pmu_pebs_data_source_nhm()
114 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in intel_pmu_pebs_data_source_nhm()
135 data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in __intel_pmu_pebs_data_source_grt()
136 data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in __intel_pmu_pebs_data_source_grt()
137 data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD); in __intel_pmu_pebs_data_source_grt()
160 data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD); in __intel_pmu_pebs_data_source_cmt()
161 data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in __intel_pmu_pebs_data_source_cmt()
[all …]
|
| /arch/arm64/boot/dts/amd/ |
| A D | amd-seattle-cpus.dtsi | 170 next-level-cache = <&L3>;
178 next-level-cache = <&L3>;
186 next-level-cache = <&L3>;
194 next-level-cache = <&L3>;
197 L3: l3-cache { label
|
| /arch/powerpc/perf/ |
| A D | isa207-common.c | 229 ret = PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in isa207_find_source()
264 ret |= PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in isa207_find_source()
266 ret |= PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in isa207_find_source()
273 ret = PH(LVL, L3) | LEVEL(L3) | REM | P(SNOOP, HIT) | P(HOPS, 0); in isa207_find_source()
275 ret = PH(LVL, L3) | LEVEL(L3) | REM | P(SNOOP, HITM) | P(HOPS, 0); in isa207_find_source()
|
| /arch/m68k/lib/ |
| A D | divsi3.S | 117 jpl L3
120 L3: movel sp@+, d2 label
|
| A D | udivsi3.S | 95 jcc L3 /* then try next algorithm */
107 L3: movel d1, d2 /* use d2 as divisor backup */ label
|
| /arch/alpha/kernel/ |
| A D | setup.c | 1196 int L1I, L1D, L2, L3; in determine_cpu_caches() local
1207 L3 = -1; in determine_cpu_caches()
1228 L3 = -1; in determine_cpu_caches()
1259 L3 = external_cache_probe(1024*1024, width); in determine_cpu_caches()
1273 L3 = -1; in determine_cpu_caches()
1296 L3 = -1; in determine_cpu_caches()
1303 L3 = -1; in determine_cpu_caches()
1308 L1I = L1D = L2 = L3 = 0; in determine_cpu_caches()
1315 alpha_l3_cacheshape = L3; in determine_cpu_caches()
|
| /arch/riscv/lib/ |
| A D | tishift.S | 33 beqz a2, .L3
44 .L3: label
|
| /arch/sparc/net/ |
| A D | bpf_jit_64.h | 23 #define L3 0x13 macro
|
| /arch/arm/boot/dts/gemini/ |
| A D | gemini-wbd111.dts | 45 label = "wbd111:red:L3";
63 label = "wbd111:green:L3";
|
| A D | gemini-wbd222.dts | 44 label = "wbd111:red:L3";
62 label = "wbd111:green:L3";
|
| /arch/arm/boot/dts/ti/omap/ |
| A D | omap4-l4-abe.dtsi | 53 /* L3 to L4 ABE mapping */
110 <0x49022000 0xff>; /* L3 Interconnect */
145 <0x49024000 0xff>; /* L3 Interconnect */
180 <0x49026000 0xff>; /* L3 Interconnect */
216 <0x4902a000 0x1000>; /* L3 data port */
252 <0x4902e000 0x7f>; /* L3 Interconnect */
314 <0x49032000 0x7f>; /* L3 Interconnect */
|
| A D | omap5-l4-abe.dtsi | 53 /* L3 to L4 ABE mapping */
110 <0x49022000 0xff>; /* L3 Interconnect */
145 <0x49024000 0xff>; /* L3 Interconnect */
180 <0x49026000 0xff>; /* L3 Interconnect */
234 <0x4902e000 0x7f>; /* L3 Interconnect */
277 <0x49032000 0x7f>; /* L3 Interconnect */
|
| A D | logicpd-torpedo-37xx-devkit.dts | 62 /* The DM3730 has a faster L3 than OMAP35, so increase pixel clock */
|
| A D | dra7-l4.dtsi | 2322 <0x45800000 0x45800000 0x400000>, /* L3 data port */
2323 <0x45c00000 0x45c00000 0x400000>, /* L3 data port */
2324 <0x46000000 0x46000000 0x400000>, /* L3 data port */
2773 <0x45800000 0x1000>; /* L3 data port */
2809 <0x45c00000 0x1000>; /* L3 data port */
2844 <0x46000000 0x1000>; /* L3 data port */
2878 <0x48436000 0x1000>; /* L3 data port */
2912 <0x4843a000 0x1000>; /* L3 data port */
2946 <0x4844c000 0x1000>; /* L3 data port */
2980 <0x48450000 0x1000>; /* L3 data port */
[all …]
|
| A D | omap3-n900.dts | 15 * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall
20 * There is "unofficial" version of bootloader which enables AES in L3 firewall
22 * There is also no runtime detection code if AES is disabled in L3 firewall...
|
| /arch/xtensa/lib/ |
| A D | memset.S | 83 bbci.l a4, 2, .L3
87 .L3: label
|
| A D | usercopy.S | 175 bbci.l a4, 2, .L3
181 .L3: label
|
| A D | memcopy.S | 161 bbsi.l a4, 2, .L3
165 .L3: label
|
| /arch/hexagon/lib/ |
| A D | memset.S | 164 if (p0.new) jump:nt .L3
176 .L3: label
|
| /arch/arm/mach-omap2/ |
| A D | sram242x.S | 86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
296 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
|
| A D | sram243x.S | 86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
296 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
|
| /arch/x86/events/amd/ |
| A D | ibs.c | 867 [IBS_DATA_SRC_LOC_CACHE] = L(L3) | L(REM_CCE1) | LN(ANY_CACHE) | HOPS(0),
877 [IBS_DATA_SRC_EXT_LOC_CACHE] = L(L3) | LN(L3),
|
| /arch/arm64/boot/dts/exynos/ |
| A D | exynosautov920.dtsi | 261 cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-0 */
270 cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-1 */
279 cache-size = <0x100000>;/* 1MB L3 cache for cpu cluster-2 */
|
| /arch/arm64/boot/dts/qcom/ |
| A D | sm8250-xiaomi-pipa.dts | 443 /* L3 & L4 are unused. */
|
| A D | sm8250-sony-xperia-edo.dtsi | 416 /* L3 & L4 are unused. */
|