| /arch/hexagon/kernel/ |
| A D | head.S | 28 r24.L = #LO(swapper_pg_dir)
40 r1.l = #LO(PAGE_OFFSET);
61 r1.l = #LO(_end);
62 r2.l = #LO(stext);
96 R1.L = #LO(PAGE_OFFSET >> (22 - 2))
187 {r29.L = #LO(init_thread_union); r0.L = #LO(_THREAD_SIZE); }
194 { r0.L = #LO(__bss_start); r1 = #0; r2.l = #LO(__bss_stop); }
202 r0.l = #LO(__phys_offset);
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| A D | vm_entry.S | 64 R2.L = #LO(_THREAD_SIZE); } \
216 R1.L = #LO(CHandler); \
281 R26.L = #LO(do_work_pending);
369 R26.L = #LO(do_work_pending);
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| /arch/arm64/crypto/ |
| A D | polyval-ce-core.S | 57 LO .req v20 label
104 eor LO.16b, LO.16b, v29.16b
122 pmull LO.1q, X.1d, Y.1d
138 eor v4.16b, v4.16b, LO.16b
140 ext v5.16b, LO.16b, HI.16b, #8
146 ext LO.16b, LO.16b, LO.16b, #8
150 ext PL.16b, LO.16b, v4.16b, #8
219 eor LO.16b, LO.16b, LO.16b
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| /arch/x86/crypto/ |
| A D | polyval-clmulni_asm.S | 34 #define LO %xmm12 macro
97 vpxor %xmm1, LO, LO
110 vpclmulqdq $0x00, %xmm0, %xmm1, LO
123 pxor LO, PL
184 pxor LO, LO
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| A D | aes-gcm-aesni-x86_64.S | 420 _vpclmulqdq $0x00, TMP0, GHASH_ACC, LO
448 pxor TMP2, LO
475 pxor LO, MI
477 pshufd $0x4e, LO, TMP2
478 pclmulqdq $0x00, TMP1, LO
480 pxor LO, MI
709 .set LO, %xmm3 // Low part of unreduced product define
850 pxor LO, LO
912 _ghash_mul_noreduce H_POW, H_POW_XORED, GHASH_ACC, LO, MI, HI, TMP0
966 _ghash_mul_noreduce H_POW, H_POW_XORED, GHASH_ACC, LO, MI, HI, TMP0
[all …]
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| A D | aes-gcm-avx10-x86_64.S | 865 .set LO, GHASHDATA0 define
926 _ghash_mul_noreduce H_POW1, V0, LO, MI, HI, GHASHDATA3, V1, V2, V3
936 _ghash_reduce LO, MI, HI, GFPOLY, V0
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| /arch/riscv/boot/dts/microchip/ |
| A D | mpfs-beaglev-fire-fabric.dtsi | 21 <0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>, /* FIC0, LO */
22 <0x0 0xe0000000 0x0 0xe0000000 0x0 0x20000000>, /* FIC1, LO */
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| /arch/arm/boot/dts/nxp/imx/ |
| A D | imx6qdl-mba6.dtsi | 516 /* 100 k PD, DSE 120 OHM, SPEED LO */
523 /* 100 k PD, DSE 120 OHM, SPEED LO */
530 /* 100 k PD, DSE 120 OHM, SPEED LO */
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| A D | mba6ulx.dtsi | 470 /* 100 k PD, DSE 120 OHM, SPEED LO */
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| /arch/hexagon/lib/ |
| A D | memcpy.S | 208 mask.l = #LO(0x7fffffff);
221 r31.l = #LO(.Lmemcpy_return); /* set up final return pointer */
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| /arch/arm64/kvm/ |
| A D | sys_regs.c | 566 if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR1_EL1, LO, IMP)) in trap_loregion()
4044 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), \
4180 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 },
4186 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 },
4199 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 },
4217 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid },
4218 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid },
4232 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 },
4236 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 },
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| A D | config.c | 90 #define FEAT_LOR ID_AA64MMFR1_EL1, LO, IMP
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| /arch/arm64/boot/dts/qcom/ |
| A D | sm8750-mtp.dts | 969 * WCD9395 RX Port 4 (LO) <=> SWR1 Port 4 (LO)
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| A D | sm8750-qrd.dts | 981 * WCD9395 RX Port 4 (LO) <=> SWR1 Port 4 (LO)
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| A D | sm8650-hdk.dts | 1185 * WCD9395 RX Port 4 (LO) <=> SWR1 Port 4 (LO)
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| A D | sm8550-hdk.dts | 1234 * WCD9385 RX Port 4 (LO) <=> SWR1 Port 4 (LO)
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| A D | sm8650-qrd.dts | 1137 * WCD9395 RX Port 4 (LO) <=> SWR1 Port 4 (LO)
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| /arch/arm64/kvm/hyp/nvhe/ |
| A D | pkvm.c | 90 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, LO, IMP)) in pvm_init_traps_hcr()
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| /arch/arm64/tools/ |
| A D | sysreg | 2209 UnsignedEnum 19:16 LO
|