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Searched refs:MHZ (Results 1 – 16 of 16) sorted by relevance

/arch/arm/mach-s3c/
A Dcpu.h45 #ifndef MHZ
46 #define MHZ (1000*1000) macro
49 #define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000)
A Dsetup-usb-phy-s3c64xx.c36 case 12 * MHZ: in s3c_usb_otgphy_init()
39 case 24 * MHZ: in s3c_usb_otgphy_init()
43 case 48 * MHZ: in s3c_usb_otgphy_init()
/arch/powerpc/boot/
A Dredboot-8xx.c19 #define MHZ(x) ((x + 500000) / 1000000) macro
32 bd.bi_busfreq, MHZ(bd.bi_busfreq)); in platform_fixups()
A Dredboot-83xx.c20 #define MHZ(x) ((x + 500000) / 1000000) macro
33 bd.bi_busfreq, MHZ(bd.bi_busfreq)); in platform_fixups()
A Ddevtree.c61 #define MHZ(x) ((x + 500000) / 1000000) macro
67 printf("CPU clock-frequency <- 0x%x (%dMHz)\n\r", cpu, MHZ(cpu)); in dt_fixup_cpu_clocks()
68 printf("CPU timebase-frequency <- 0x%x (%dMHz)\n\r", tb, MHZ(tb)); in dt_fixup_cpu_clocks()
70 printf("CPU bus-frequency <- 0x%x (%dMHz)\n\r", bus, MHZ(bus)); in dt_fixup_cpu_clocks()
87 printf("%s: clock-frequency <- %x (%dMHz)\n\r", path, freq, MHZ(freq)); in dt_fixup_clock()
/arch/arm64/boot/dts/qcom/
A Dipq9574-rdp-common.dtsi220 * (48 MHZ or 96 MHZ used for different RDP type board). This setting
222 * clock output from WiFi to the CMN PLL is 48 MHZ.
230 * The frequency of xo_board_clk is fixed to 24 MHZ, which is routed
231 * from WiFi output clock 48 MHZ divided by 2.
/arch/arc/boot/dts/
A Dhaps_hs_idu.dts40 clock-frequency = <50000000>; /* 50 MHZ */
/arch/arm/boot/dts/nvidia/
A Dtegra30-asus-tf300t.dts147 /* Elpida 1GB 667MHZ */
212 /* Hynix 1GB 667MHZ */
277 /* Micron 1GB 667MHZ */
344 /* Elpida 1GB 667MHZ */
562 /* Hynix 1GB 667MHZ */
780 /* Micron 1GB 667MHZ */
A Dtegra30-asus-tf300tg.dts221 /* Elpida 1GB 667MHZ */
286 /* Hynix 1GB 667MHZ */
351 /* Micron 1GB 667MHZ */
418 /* Elpida 1GB 667MHZ */
636 /* Hynix 1GB 667MHZ */
854 /* Micron 1GB 667MHZ */
A Dtegra30-asus-tf300tl.dts241 /* Elpida 1GB 667MHZ */
306 /* Hynix 1GB 667MHZ */
373 /* Elpida 1GB 667MHZ */
591 /* Hynix 1GB 667MHZ */
A Dtegra30-asus-tf700t.dts142 /* Micron 1GB 800MHZ */
207 /* Elpida 1GB 800MHZ */
274 /* Micron 1GB 800MHZ */
492 /* Elpida 1GB 800MHZ */
A Dtegra30-asus-tf201.dts168 /* TF201 Unknown 1GB LPDDR2 500MHZ */
405 /* TF201 Unknown 1GB LPDDR2 500MHZ */
A Dtegra30-asus-tf600t.dts1289 /* Elpida 2GB 750 MHZ */
1354 /* Hynix 2GB 750 MHZ */
1409 /* Micron 2GB 750 MHZ */
1466 /* Elpida 2GB 750 MHZ */
1684 /* Hynix 2GB 750 MHZ */
1866 /* Micron 2GB 750 MHZ */
/arch/arm64/boot/dts/freescale/
A Dimx8ulp-evk.dts86 /* External ts clock is 50MHZ from PHY on EVK board. */
/arch/arm/boot/dts/nxp/imx/
A Dimx6qdl-ts4900.dtsi179 MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x10 /* FPGA 24MHZ */
A Dimx6qdl-ts7970.dtsi277 MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x10 /* FPGA 24MHZ */

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