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Searched refs:MSR_P4_CRU_ESCR0 (Results 1 – 2 of 2) sorted by relevance

/arch/x86/events/intel/
A Dp4.c439 .escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
449 .escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
475 .escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
502 .escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
1171 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR0),
/arch/x86/include/asm/
A Dmsr-index.h1123 #define MSR_P4_CRU_ESCR0 0x000003b8 macro

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