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Searched refs:MSR_P6_EVNTSEL0 (Results 1 – 6 of 6) sorted by relevance

/arch/x86/events/intel/
A Dp6.c146 rdmsrq(MSR_P6_EVNTSEL0, val); in p6_pmu_disable_all()
148 wrmsrq(MSR_P6_EVNTSEL0, val); in p6_pmu_disable_all()
156 rdmsrq(MSR_P6_EVNTSEL0, val); in p6_pmu_enable_all()
158 wrmsrq(MSR_P6_EVNTSEL0, val); in p6_pmu_enable_all()
213 .eventsel = MSR_P6_EVNTSEL0,
/arch/x86/kernel/cpu/
A Dperfctr-watchdog.c93 return msr - MSR_P6_EVNTSEL0; in nmi_evntsel_msr_to_bit()
/arch/x86/xen/
A Dpmu.c179 if ((msr_index >= MSR_P6_EVNTSEL0) && in is_intel_pmu_msr()
180 (msr_index < MSR_P6_EVNTSEL0 + intel_num_arch_counters)) { in is_intel_pmu_msr()
181 *index = msr_index - MSR_P6_EVNTSEL0; in is_intel_pmu_msr()
/arch/x86/kvm/vmx/
A Dpmu_intel.c208 get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0) || in intel_is_valid_msr()
223 pmc = pmc ? pmc : get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0); in intel_msr_idx_to_pmc()
371 } else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) { in intel_pmu_get_msr()
436 } else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) { in intel_pmu_set_msr()
/arch/x86/include/asm/
A Dmsr-index.h588 #define MSR_P6_EVNTSEL0 0x00000186 macro
/arch/x86/kvm/
A Dx86.c4075 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: in kvm_set_msr_common()
4253 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: in kvm_get_msr_common()

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