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Searched refs:MSR_TYPE_RW (Results 1 – 6 of 6) sorted by relevance

/arch/x86/kvm/vmx/
A Dpmu_intel.c681 vmx_set_intercept_for_msr(vcpu, lbr->from + i, MSR_TYPE_RW, set); in vmx_update_intercept_for_lbr_msrs()
682 vmx_set_intercept_for_msr(vcpu, lbr->to + i, MSR_TYPE_RW, set); in vmx_update_intercept_for_lbr_msrs()
684 vmx_set_intercept_for_msr(vcpu, lbr->info + i, MSR_TYPE_RW, set); in vmx_update_intercept_for_lbr_msrs()
687 vmx_set_intercept_for_msr(vcpu, MSR_LBR_SELECT, MSR_TYPE_RW, set); in vmx_update_intercept_for_lbr_msrs()
688 vmx_set_intercept_for_msr(vcpu, MSR_LBR_TOS, MSR_TYPE_RW, set); in vmx_update_intercept_for_lbr_msrs()
A Dvmx.c2196 MSR_TYPE_RW); in vmx_set_msr()
2289 MSR_TYPE_RW); in vmx_set_msr()
4043 vmx_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW, in vmx_update_msr_bitmap_x2apic()
4078 vmx_disable_intercept_for_msr(vcpu, MSR_FS_BASE, MSR_TYPE_RW); in vmx_recalc_msr_intercepts()
4079 vmx_disable_intercept_for_msr(vcpu, MSR_GS_BASE, MSR_TYPE_RW); in vmx_recalc_msr_intercepts()
4080 vmx_disable_intercept_for_msr(vcpu, MSR_KERNEL_GS_BASE, MSR_TYPE_RW); in vmx_recalc_msr_intercepts()
4082 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW); in vmx_recalc_msr_intercepts()
4083 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW); in vmx_recalc_msr_intercepts()
4084 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW); in vmx_recalc_msr_intercepts()
4101 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_XFD, MSR_TYPE_RW); in vmx_recalc_msr_intercepts()
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A Dnested.c701 MSR_FS_BASE, MSR_TYPE_RW); in nested_vmx_prepare_msr_bitmap()
704 MSR_GS_BASE, MSR_TYPE_RW); in nested_vmx_prepare_msr_bitmap()
707 MSR_KERNEL_GS_BASE, MSR_TYPE_RW); in nested_vmx_prepare_msr_bitmap()
710 MSR_IA32_SPEC_CTRL, MSR_TYPE_RW); in nested_vmx_prepare_msr_bitmap()
/arch/x86/kvm/svm/
A Dsvm.c783 MSR_TYPE_RW, intercept); in svm_set_x2apic_msr_interception()
797 svm_disable_intercept_for_msr(vcpu, MSR_STAR, MSR_TYPE_RW); in svm_recalc_msr_intercepts()
801 svm_disable_intercept_for_msr(vcpu, MSR_GS_BASE, MSR_TYPE_RW); in svm_recalc_msr_intercepts()
802 svm_disable_intercept_for_msr(vcpu, MSR_FS_BASE, MSR_TYPE_RW); in svm_recalc_msr_intercepts()
804 svm_disable_intercept_for_msr(vcpu, MSR_LSTAR, MSR_TYPE_RW); in svm_recalc_msr_intercepts()
805 svm_disable_intercept_for_msr(vcpu, MSR_CSTAR, MSR_TYPE_RW); in svm_recalc_msr_intercepts()
806 svm_disable_intercept_for_msr(vcpu, MSR_SYSCALL_MASK, MSR_TYPE_RW); in svm_recalc_msr_intercepts()
827 svm_set_intercept_for_msr(vcpu, MSR_IA32_SPEC_CTRL, MSR_TYPE_RW, in svm_recalc_msr_intercepts()
830 svm_set_intercept_for_msr(vcpu, MSR_IA32_SPEC_CTRL, MSR_TYPE_RW, in svm_recalc_msr_intercepts()
837 svm_set_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW, in svm_recalc_msr_intercepts()
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A Dsev.c4446 svm_disable_intercept_for_msr(vcpu, MSR_AMD64_SEV_ES_GHCB, MSR_TYPE_RW); in sev_es_recalc_msr_intercepts()
4447 svm_disable_intercept_for_msr(vcpu, MSR_EFER, MSR_TYPE_RW); in sev_es_recalc_msr_intercepts()
4448 svm_disable_intercept_for_msr(vcpu, MSR_IA32_CR_PAT, MSR_TYPE_RW); in sev_es_recalc_msr_intercepts()
4451 svm_set_intercept_for_msr(vcpu, MSR_TSC_AUX, MSR_TYPE_RW, in sev_es_recalc_msr_intercepts()
4467 svm_set_intercept_for_msr(vcpu, MSR_IA32_XSS, MSR_TYPE_RW, in sev_es_recalc_msr_intercepts()
/arch/x86/kvm/
A Dx86.h624 MSR_TYPE_RW = MSR_TYPE_R | MSR_TYPE_W, enumerator

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