Searched refs:OP2 (Results 1 – 5 of 5) sorted by relevance
| /arch/arm/kernel/ |
| A D | hw_breakpoint.c | 50 case ((OP2 << 4) + M): \
55 case ((OP2 << 4) + M): \
60 READ_WB_REG_CASE(OP2, 0, VAL); \
61 READ_WB_REG_CASE(OP2, 1, VAL); \
62 READ_WB_REG_CASE(OP2, 2, VAL); \
63 READ_WB_REG_CASE(OP2, 3, VAL); \
64 READ_WB_REG_CASE(OP2, 4, VAL); \
65 READ_WB_REG_CASE(OP2, 5, VAL); \
66 READ_WB_REG_CASE(OP2, 6, VAL); \
75 READ_WB_REG_CASE(OP2, 15, VAL)
[all …]
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| /arch/arm/include/asm/ |
| A D | hw_breakpoint.h | 110 #define ARM_DBG_READ(N, M, OP2, VAL) do {\ argument
111 asm volatile("mrc p14, 0, %0, " #N "," #M ", " #OP2 : "=r" (VAL));\
114 #define ARM_DBG_WRITE(N, M, OP2, VAL) do {\ argument
115 asm volatile("mcr p14, 0, %0, " #N "," #M ", " #OP2 : : "r" (VAL));\
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| /arch/arm64/include/uapi/asm/ |
| A D | kvm.h | 253 ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
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| /arch/sparc/net/ |
| A D | bpf_jit_comp_32.c | 29 #define OP2(X) ((X) << 22) macro
33 #define F2(X, Y) (OP(X) | OP2(Y))
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| A D | bpf_jit_comp_64.c | 58 #define OP2(X) ((X) << 22) macro
63 #define F2(X, Y) (OP(X) | OP2(Y))
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