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/arch/x86/events/intel/
A Dds.c84 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
91 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
199 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA), /* 0x00: ukn L3 */
214 …P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x0f: L3 Miss Snoop HitM…
234 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2); in precise_store_data()
305 *val |= P(TLB, MISS) | P(TLB, L2); in pebs_set_tlb_lock()
307 *val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2); in pebs_set_tlb_lock()
369 val = P(OP, LOAD) | LEVEL(NA) | P(SNOOP, NA); in lnc_latency_data()
372 val |= P(TLB, MISS) | P(TLB, L2); in lnc_latency_data()
374 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2); in lnc_latency_data()
[all …]
/arch/powerpc/perf/
A Disa207-common.c233 ret = P(SNOOP, HIT); in isa207_find_source()
252 ret |= P(SNOOP, HIT); in isa207_find_source()
269 ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HIT) | P(HOPS, 0); in isa207_find_source()
271 ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HITM) | P(HOPS, 0); in isa207_find_source()
273 ret = PH(LVL, L3) | LEVEL(L3) | REM | P(SNOOP, HIT) | P(HOPS, 0); in isa207_find_source()
275 ret = PH(LVL, L3) | LEVEL(L3) | REM | P(SNOOP, HITM) | P(HOPS, 0); in isa207_find_source()
282 P(SNOOP, HIT) | P(HOPS, 2); in isa207_find_source()
285 P(SNOOP, HITM) | P(HOPS, 2); in isa207_find_source()
288 P(SNOOP, HIT) | P(HOPS, 3); in isa207_find_source()
291 P(SNOOP, HITM) | P(HOPS, 3); in isa207_find_source()
[all …]
A Disa207-common.h274 #define P(a, b) PERF_MEM_S(a, b) macro
275 #define PH(a, b) (P(LVL, HIT) | P(a, b))
276 #define PM(a, b) (P(LVL, MISS) | P(a, b))
277 #define LEVEL(x) P(LVLNUM, x)
278 #define REM P(REMOTE, REMOTE)
/arch/alpha/include/asm/
A Dswitch_to.h9 #define switch_to(P,N,L) \ argument
11 (L) = alpha_switch_to(virt_to_phys(&task_thread_info(N)->pcb), (P)); \
/arch/arm/boot/dts/ti/omap/
A Domap4-l4.dtsi56 /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
156 /* Domains (V, P, C): core, core_pwrdm, l3_dma_clkdm */
332 /* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */
474 /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */
495 /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */
589 /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
628 /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
665 /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
733 /* Domains (V, P, C): core, cam_pwrdm, iss_clkdm */
2011 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
[all …]
A Dam437x-l4.dtsi705 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
732 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
762 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
792 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
833 /* Domains (P, C): per_pwrdm, l3s_clkdm */
864 /* Domains (P, C): per_pwrdm, l3s_clkdm */
898 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
925 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
951 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
978 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
[all …]
A Domap5-l4.dtsi185 /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
233 /* Domains (V, P, C): core, core_pwrdm, dma_clkdm */
362 /* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */
605 /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */
644 /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */
1074 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1100 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1128 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1156 /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
1807 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
[all …]
A Domap4-l4-abe.dtsi99 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
134 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
169 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
203 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
241 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
274 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
300 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
334 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
365 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
396 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
[all …]
A Ddra7-l4.dtsi210 /* Domains (P, C): core_pwrdm, dma_clkdm */
451 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
484 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
1591 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
1845 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
2760 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3335 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3362 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3389 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3416 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
[all …]
A Domap5-l4-abe.dtsi99 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
134 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
169 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
223 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
263 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
297 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
329 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
361 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
392 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
452 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
A Dam33xx-l4.dtsi1103 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1134 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1167 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1197 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1228 /* Domains (P, C): per_pwrdm, l3s_clkdm */
1258 /* Domains (P, C): per_pwrdm, l3s_clkdm */
1291 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1318 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1343 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1369 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
[all …]
/arch/arm64/boot/dts/apple/
A Dt8011.dtsi40 i-cache-size = <0x10000>; /* P-core */
41 d-cache-size = <0x10000>; /* P-core */
53 i-cache-size = <0x10000>; /* P-core */
54 d-cache-size = <0x10000>; /* P-core */
66 i-cache-size = <0x10000>; /* P-core */
67 d-cache-size = <0x10000>; /* P-core */
74 cache-size = <0x800000>; /* P-cluster */
A Dt8010.dtsi40 i-cache-size = <0x10000>; /* P-core */
41 d-cache-size = <0x10000>; /* P-core */
53 i-cache-size = <0x10000>; /* P-core */
54 d-cache-size = <0x10000>; /* P-core */
61 cache-size = <0x300000>; /* P-cluster */
A Dt8012.dtsi40 i-cache-size = <0x10000>; /* P-core */
41 d-cache-size = <0x10000>; /* P-core */
53 i-cache-size = <0x10000>; /* P-core */
54 d-cache-size = <0x10000>; /* P-core */
61 cache-size = <0x300000>; /* P-cluster */
/arch/mips/kernel/
A Dperf_event_mipsxx.c67 P = 2, enumerator
1045 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
1412 [C(RESULT_MISS)] = { 28, CNTR_ODD, P },
1416 [C(RESULT_MISS)] = { 28, CNTR_ODD, P },
1722 raw_event.range = P; in mipsxx_pmu_map_raw_event()
1733 raw_event.range = P; in mipsxx_pmu_map_raw_event()
1748 raw_event.range = P; in mipsxx_pmu_map_raw_event()
1758 raw_event.range = P; in mipsxx_pmu_map_raw_event()
1772 raw_event.range = P; in mipsxx_pmu_map_raw_event()
1789 raw_event.range = P; in mipsxx_pmu_map_raw_event()
[all …]
/arch/arm/boot/dts/nxp/imx/
A Dimx6qdl-dhcom-drc02.dtsi86 * controlled by DHCOM GPIO P. So remove rts/cts pins and the property
87 * uart-has-rtscts from this UART and add the DHCOM GPIO P pin via
95 rts-gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; /* GPIO P */
122 * P: uart5 rs485-tx-en
A Dimx6q-kp-tpc.dts12 model = "Freescale i.MX6 Qwuad K+P TPC Board";
A Dimx6ull-dhcom-drc02.dts51 "DHCOM-R", "DHCOM-Q", "DHCOM-P", "DHCOM-O",
98 rts-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* GPIO P */
A Dimx53-kp-hsc.dts11 model = "K+P imx53 HSC";
/arch/arm/boot/dts/intel/pxa/
A Dpxa2xx.dtsi13 groups = PMGROUP(P ## pin); \
18 groups = PMGROUP(P ## pin); \
24 groups = PMGROUP(P ## pin); \
/arch/arm64/boot/dts/freescale/
A Dimx8mp-dhcom-drc02.dts197 * controlled by DHCOM GPIO P. So remove RTS/CTS pins and the property
198 * uart-has-rtscts from this UART and add the DHCOM GPIO P pin via
206 rts-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; /* GPIO P */
245 * GPIO P is connected to RS485_TX_En
/arch/m68k/fpsp040/
A Dstwotox.S61 | 3. Calculate P where 1 + P approximates exp(r):
62 | P = r + r*r*(A1+r*(A2+...+r*A5)).
/arch/arm/boot/dts/nvidia/
A Dtegra30-asus-nexus7-tilapia.dtsi15 <TEGRA_GPIO(P, 1) GPIO_ACTIVE_HIGH>,
213 enable-gpios = <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
214 firmware-gpios = <&gpio TEGRA_GPIO(P, 3) GPIO_ACTIVE_HIGH>;
/arch/arm/boot/dts/aspeed/
A Daspeed-bmc-delta-ahe50dc.dts62 gpios = <&gpio ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
67 gpios = <&gpio ASPEED_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
378 /* P */ "LED_GREEN", "", "LED_RED", "", "", "", "", "",
/arch/arm64/boot/dts/allwinner/
A Dsun50i-h6-gpu-opp.dtsi2 // Copyright (C) 2022 Clément Péron <peron.clem@gmail.com>

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