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Searched refs:PTR_WD (Results 1 – 19 of 19) sorted by relevance

/arch/mips/include/asm/
A Dunaligned-emul.h23 STR(PTR_WD)"\t1b, 4b\n\t" \
24 STR(PTR_WD)"\t2b, 4b\n\t" \
77 STR(PTR_WD)"\t1b, 11b\n\t" \
78 STR(PTR_WD)"\t2b, 11b\n\t" \
79 STR(PTR_WD)"\t3b, 11b\n\t" \
80 STR(PTR_WD)"\t4b, 11b\n\t" \
181 STR(PTR_WD)"\t1b, 11b\n\t" \
182 STR(PTR_WD)"\t2b, 11b\n\t" \
183 STR(PTR_WD)"\t3b, 11b\n\t" \
184 STR(PTR_WD)"\t4b, 11b\n\t" \
[all …]
A Dftrace.h35 STR(PTR_WD) "\t1b, 3b\n\t" \
57 STR(PTR_WD) "\t1b, 3b\n\t" \
A Dasm.h291 #define PTR_WD .word macro
316 #define PTR_WD .dword macro
A Dr4kcache.h126 " "STR(PTR_WD)" 1b, 3b \n" \
149 " "STR(PTR_WD)" 1b, 3b \n" \
/arch/mips/kernel/
A Drelocate_kernel.S148 arg0: PTR_WD 0x0
149 arg1: PTR_WD 0x0
150 arg2: PTR_WD 0x0
151 arg3: PTR_WD 0x0
161 s_arg0: PTR_WD 0x0
162 s_arg1: PTR_WD 0x0
163 s_arg2: PTR_WD 0x0
164 s_arg3: PTR_WD 0x0
172 PTR_WD 0x0
176 PTR_WD 0
[all …]
A Dmips-r2-to-r6-emul.c1261 STR(PTR_WD) " 1b,8b\n" in mipsr2_decoder()
1262 STR(PTR_WD) " 2b,8b\n" in mipsr2_decoder()
1263 STR(PTR_WD) " 3b,8b\n" in mipsr2_decoder()
1264 STR(PTR_WD) " 4b,8b\n" in mipsr2_decoder()
1336 STR(PTR_WD) " 1b,8b\n" in mipsr2_decoder()
1337 STR(PTR_WD) " 2b,8b\n" in mipsr2_decoder()
1338 STR(PTR_WD) " 3b,8b\n" in mipsr2_decoder()
1339 STR(PTR_WD) " 4b,8b\n" in mipsr2_decoder()
1407 STR(PTR_WD) " 1b,8b\n" in mipsr2_decoder()
1408 STR(PTR_WD) " 2b,8b\n" in mipsr2_decoder()
[all …]
A Dsyscall.c126 " "STR(PTR_WD)" 1b, 4b \n" in mips_atomic_set()
127 " "STR(PTR_WD)" 2b, 4b \n" in mips_atomic_set()
156 " "STR(PTR_WD)" 1b, 5b \n" in mips_atomic_set()
157 " "STR(PTR_WD)" 2b, 5b \n" in mips_atomic_set()
A Dscall32-o32.S74 PTR_WD load_a4, bad_stack_a4
75 PTR_WD load_a5, bad_stack_a5
76 PTR_WD load_a6, bad_stack_a6
77 PTR_WD load_a7, bad_stack_a7
221 #define __SYSCALL(nr, entry) PTR_WD entry
A Dscall64-o32.S76 PTR_WD load_a4, bad_stack_a4
77 PTR_WD load_a5, bad_stack_a5
78 PTR_WD load_a6, bad_stack_a6
79 PTR_WD load_a7, bad_stack_a7
218 #define __SYSCALL(nr, entry) PTR_WD entry
A Dr2300_fpu.S26 PTR_WD 9b,fault; \
32 PTR_WD 9b,fault; \
33 PTR_WD 9b+4,fault; \
A Dscall64-n32.S105 #define __SYSCALL(nr, entry) PTR_WD entry
A Dscall64-n64.S112 #define __SYSCALL(nr, entry) PTR_WD entry
A Dr4k_fpu.S34 PTR_WD .ex\@, fault
/arch/mips/lib/
A Dstrncpy_user.S18 PTR_WD 9b, handler; \
62 PTR_WD 1b, .Lfault
A Dstrnlen_user.S17 PTR_WD 9b, handler; \
A Dmemcpy.S119 PTR_WD 9b, handler; \
128 PTR_WD 9b, handler; \
A Dmemset.S55 PTR_WD 9b, handler; \
A Dcsum_partial.S350 PTR_WD 9b, .L_exc; \
359 PTR_WD 9b, .L_exc; \
/arch/mips/cavium-octeon/
A Docteon-memcpy.S77 PTR_WD 9b, handler; \

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