| /arch/hexagon/kernel/ |
| A D | vm_entry.S | 70 R2 = and(R0,R2); } \
215 R0 = R29; \
232 R0 = usr; \
236 R0 = setbit(R0, #16); \
238 usr = R0; \
246 R0 = R29; \
274 R0 = #VM_INT_DISABLE define
287 R0 = #VM_INT_DISABLE; define
308 R0 = #VM_INT_DISABLE; define
331 R0 = R29 define
[all …]
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| A D | vm_switch.S | 55 memw(R0+#_TASK_THREAD_INFO) = THREADINFO_REG;
56 memw(R0 +#(_TASK_STRUCT_THREAD + _THREAD_STRUCT_SWITCH_SP)) = R29;
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| A D | head.S | 153 memw(R1 ++ #4) = R0
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| /arch/x86/crypto/ |
| A D | twofish-x86_64-asm_64.S | 30 #define R0 %rax macro
227 encrypt_round(R0,R1,R2,R3,0);
228 encrypt_round(R2,R3,R0,R1,8);
229 encrypt_round(R0,R1,R2,R3,2*8);
230 encrypt_round(R2,R3,R0,R1,3*8);
231 encrypt_round(R0,R1,R2,R3,4*8);
232 encrypt_round(R2,R3,R0,R1,5*8);
233 encrypt_round(R0,R1,R2,R3,6*8);
234 encrypt_round(R2,R3,R0,R1,7*8);
249 xor R0, R1
[all …]
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| A D | twofish-i586-asm_32.S | 231 encrypt_round(R0,R1,R2,R3,0);
232 encrypt_round(R2,R3,R0,R1,8);
233 encrypt_round(R0,R1,R2,R3,2*8);
234 encrypt_round(R2,R3,R0,R1,3*8);
235 encrypt_round(R0,R1,R2,R3,4*8);
236 encrypt_round(R2,R3,R0,R1,5*8);
237 encrypt_round(R0,R1,R2,R3,6*8);
238 encrypt_round(R2,R3,R0,R1,7*8);
239 encrypt_round(R0,R1,R2,R3,8*8);
240 encrypt_round(R2,R3,R0,R1,9*8);
[all …]
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| /arch/sh/kernel/cpu/sh3/ |
| A D | swsusp.S | 59 ! BL=0: R7->R0 is bank0
65 ! BL=1: R7->R0 is bank1
80 ! BL=0: R7->R0 is bank0
105 ! BL=0: R7->R0 is bank0
112 ! BL=1: R7->R0 is bank1
119 ! BL=0: R7->R0 is bank0
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| /arch/sh/math-emu/ |
| A D | math.c | 52 #define R0 (regs->regs[0]) macro
162 MREAD(FRn, Rm + R0 + 4); in fmov_idx_reg()
164 MREAD(FRn, Rm + R0); in fmov_idx_reg()
166 MREAD(FRn, Rm + R0); in fmov_idx_reg()
212 MWRITE(FRm, Rn + R0 + 4); in fmov_reg_idx()
214 MWRITE(FRm, Rn + R0); in fmov_reg_idx()
216 MWRITE(FRm, Rn + R0); in fmov_reg_idx()
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| /arch/powerpc/mm/nohash/ |
| A D | tlb_low.S | 219 PPC_TLBILX_ALL(0,R0)
232 PPC_TLBILX_PID(0,R0)
284 PPC_TLBILX_PID(0,R0)
296 PPC_TLBILX_PID(0,R0)
303 PPC_TLBILX_ALL(0,R0)
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| /arch/arm/include/asm/vdso/ |
| A D | cp15.h | 17 "mrrc", "mcrr", __stringify(p15, Op1, %Q0, %R0, CRm), u64
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| /arch/powerpc/kernel/ |
| A D | misc_64.S | 152 LBZCIX(R3,R0,R3)
167 STBCIX(R3,R0,R4)
301 PPC_TLBILX_ALL(0,R0)
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| /arch/arm/boot/dts/st/ |
| A D | ste-ux500-samsung-codina.dts | 6 * as "R0.0". There appears to be a "R0.4" variant with backlight on GPIO69,
239 * GPIO194 on R0.0, R0.4 does not use this at all, it
241 * (Line is pulled down on R0.4)
251 * GPIO68 is for R0.0, the board file talks about a TMO variant
252 * (R0.4) using GPIO69.
684 * This will make the resistor mounted in R0.0 pull up
686 * GPIO input mode, no pull-up. On R0.4 variants, GPIO130
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| /arch/powerpc/lib/ |
| A D | ldstfp.S | 169 1: LXVD2X(0,R0,R4)
198 STXVD2X(0,R0,R4)
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| /arch/powerpc/kvm/ |
| A D | book3s_64_entry.S | 238 ld r0,VCPU_GPR(R0)(r3)
310 std r0,VCPU_GPR(R0)(r3)
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| A D | booke_interrupts.S | 207 stw r0, VCPU_GPR(R0)(r4)
415 lwz r0, VCPU_GPR(R0)(r4)
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| /arch/arm/boot/dts/aspeed/ |
| A D | aspeed-bmc-qcom-dc-scm-v1.dts | 112 /*R0-R7*/ "","","","","","","","",
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| A D | aspeed-bmc-vegman-n110.dts | 32 /*R0-R7*/ "_SPI_RMM4_LITE_CS","","","","","","","",
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| A D | aspeed-bmc-vegman-sx20.dts | 32 /*R0-R7*/ "_SPI_RMM4_LITE_CS","","","","","","","",
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| A D | aspeed-bmc-amd-daytonax.dts | 143 /*R0-R7*/ "","","","","","","","",
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| A D | aspeed-bmc-inventec-transformers.dts | 288 /*R0-R7*/ "","","","","","","","",
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| A D | aspeed-bmc-amd-ethanolx.dts | 145 /*R0-R7*/ "","","","","","","","",
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| A D | aspeed-bmc-opp-romulus.dts | 253 /*R0-R7*/ "","","fsi-trans","","","led-power","","",
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| A D | aspeed-bmc-facebook-greatlakes.dts | 272 /*R0-R7*/ "","","","","","","","",
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| A D | aspeed-bmc-opp-nicole.dts | 237 /*R0-R7*/ "","software_pwrgood","","","","","","",
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| A D | aspeed-bmc-ufispace-ncplite.dts | 355 /*R0-R7*/ "","","","","","","","",
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| /arch/arm/kernel/ |
| A D | entry-ftrace.S | 83 @ R0 | R1 | ... | IP | SP + 4 | previous LR | LR | PSR | OLD_R0 |
|