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Searched refs:RD (Results 1 – 25 of 26) sorted by relevance

12

/arch/x86/crypto/
A Dserpent-sse2-i586-asm_32.S516 S0(RA, RB, RC, RD, RE); LK(RC, RB, RD, RA, RE, 1);
517 S1(RC, RB, RD, RA, RE); LK(RE, RD, RA, RC, RB, 2);
518 S2(RE, RD, RA, RC, RB); LK(RB, RD, RE, RC, RA, 3);
519 S3(RB, RD, RE, RC, RA); LK(RC, RA, RD, RB, RE, 4);
520 S4(RC, RA, RD, RB, RE); LK(RA, RD, RB, RE, RC, 5);
521 S5(RA, RD, RB, RE, RC); LK(RC, RA, RD, RE, RB, 6);
522 S6(RC, RA, RD, RE, RB); LK(RD, RB, RA, RE, RC, 7);
523 S7(RD, RB, RA, RE, RC); LK(RC, RA, RE, RD, RB, 8);
524 S0(RC, RA, RE, RD, RB); LK(RE, RA, RD, RC, RB, 9);
601 SI1(RE, RD, RB, RC, RA); KL(RA, RD, RB, RC, RE, 9);
[all …]
A Dserpent-sse2-x86_64-asm_64.S637 S(S0, RA, RB, RC, RD, RE); LK2(RC, RB, RD, RA, RE, 1);
638 S(S1, RC, RB, RD, RA, RE); LK2(RE, RD, RA, RC, RB, 2);
639 S(S2, RE, RD, RA, RC, RB); LK2(RB, RD, RE, RC, RA, 3);
640 S(S3, RB, RD, RE, RC, RA); LK2(RC, RA, RD, RB, RE, 4);
641 S(S4, RC, RA, RD, RB, RE); LK2(RA, RD, RB, RE, RC, 5);
642 S(S5, RA, RD, RB, RE, RC); LK2(RC, RA, RD, RE, RB, 6);
643 S(S6, RC, RA, RD, RE, RB); LK2(RD, RB, RA, RE, RC, 7);
644 S(S7, RD, RB, RA, RE, RC); LK2(RC, RA, RE, RD, RB, 8);
645 S(S0, RC, RA, RE, RD, RB); LK2(RE, RA, RD, RC, RB, 9);
646 S(S1, RE, RA, RD, RC, RB); LK2(RB, RD, RC, RE, RA, 10);
[all …]
A Dserpent-avx-x86_64-asm_64.S568 S(S0, RA, RB, RC, RD, RE); LK2(RC, RB, RD, RA, RE, 1);
569 S(S1, RC, RB, RD, RA, RE); LK2(RE, RD, RA, RC, RB, 2);
570 S(S2, RE, RD, RA, RC, RB); LK2(RB, RD, RE, RC, RA, 3);
571 S(S3, RB, RD, RE, RC, RA); LK2(RC, RA, RD, RB, RE, 4);
572 S(S4, RC, RA, RD, RB, RE); LK2(RA, RD, RB, RE, RC, 5);
573 S(S5, RA, RD, RB, RE, RC); LK2(RC, RA, RD, RE, RB, 6);
574 S(S6, RC, RA, RD, RE, RB); LK2(RD, RB, RA, RE, RC, 7);
575 S(S7, RD, RB, RA, RE, RC); LK2(RC, RA, RE, RD, RB, 8);
576 S(S0, RC, RA, RE, RD, RB); LK2(RE, RA, RD, RC, RB, 9);
577 S(S1, RE, RA, RD, RC, RB); LK2(RB, RD, RC, RE, RA, 10);
[all …]
A Dserpent-avx2-asm_64.S567 S(S0, RA, RB, RC, RD, RE); LK2(RC, RB, RD, RA, RE, 1);
568 S(S1, RC, RB, RD, RA, RE); LK2(RE, RD, RA, RC, RB, 2);
569 S(S2, RE, RD, RA, RC, RB); LK2(RB, RD, RE, RC, RA, 3);
570 S(S3, RB, RD, RE, RC, RA); LK2(RC, RA, RD, RB, RE, 4);
571 S(S4, RC, RA, RD, RB, RE); LK2(RA, RD, RB, RE, RC, 5);
572 S(S5, RA, RD, RB, RE, RC); LK2(RC, RA, RD, RE, RB, 6);
573 S(S6, RC, RA, RD, RE, RB); LK2(RD, RB, RA, RE, RC, 7);
574 S(S7, RD, RB, RA, RE, RC); LK2(RC, RA, RE, RD, RB, 8);
575 S(S0, RC, RA, RE, RD, RB); LK2(RE, RA, RD, RC, RB, 9);
576 S(S1, RE, RA, RD, RC, RB); LK2(RB, RD, RC, RE, RA, 10);
[all …]
A Dtwofish-avx-x86_64-asm_64.S189 encrypt_round((2*n), RA, RB, RC, RD, preload_rgi, rotate_1l); \
190 encrypt_round(((2*n) + 1), RC, RD, RA, RB, preload_rgi, rotate_1l);
193 encrypt_round((2*n), RA, RB, RC, RD, preload_rgi, rotate_1l); \
194 encrypt_round(((2*n) + 1), RC, RD, RA, RB, dummy, dummy);
197 decrypt_round(((2*n) + 1), RC, RD, RA, RB, preload_rgi, rotate_1l); \
198 decrypt_round((2*n), RA, RB, RC, RD, preload_rgi, rotate_1l);
201 decrypt_round(((2*n) + 1), RC, RD, RA, RB, preload_rgi, rotate_1l); \
202 decrypt_round((2*n), RA, RB, RC, RD, dummy, dummy);
A Dcast6-avx-x86_64-asm_64.S157 qop(RD, RC, 1); \
166 qop(RA, RD, 1);
170 qop(RA, RD, 1); \
179 qop(RD, RC, 1);
/arch/mips/mm/
A Duasm-mips.c72 [insn_cfc1] = {M(cop1_op, cfc_op, 0, 0, 0, 0), RT | RD},
80 RS | RT | RD},
87 RS | RT | RD},
90 RS | RT | RD},
94 RS | RT | RD},
141 [insn_mfhi] = {M(spec_op, 0, 0, 0, 0, mfhi_op), RD},
142 [insn_mflo] = {M(spec_op, 0, 0, 0, 0, mflo_op), RD},
144 RS | RT | RD},
152 RS | RT | RD},
154 RS | RT | RD},
[all …]
A Duasm-micromips.c43 [insn_addu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD},
45 [insn_and] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD},
93 [insn_mul] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD},
94 [insn_or] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD},
101 [insn_sll] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD},
103 [insn_slt] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_slt_op), RT | RS | RD},
105 [insn_sltu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sltu_op), RT | RS | RD},
106 [insn_sra] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD},
107 [insn_srav] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srav_op), RT | RS | RD},
108 [insn_srl] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD},
[all …]
A Duasm.c19 RD = 0x004, enumerator
/arch/sparc/include/asm/
A Dopcodes.h14 #define RD(x) (FPD_ENCODE(x) << 25) macro
19 .word (F3F(2,0x36,0x147)|RS1(a)|RS2(b)|RD(c));
31 .word (F3F(2, 0x19, 0)|RS1(a)|RS2(b)|RS3(c)|RD(d));
33 .word (F3F(2, 0x19, 1)|RS1(a)|RS2(b)|RS3(c)|RD(d));
35 .word (F3F(2, 0x19, 2)|RS1(a)|RS2(b)|RS3(c)|RD(d));
37 .word (F3F(2, 0x19, 3)|RS1(a)|RS2(b)|RS3(c)|RD(d));
49 .word (F3F(2, 0x36, 0x130)|RS1(a)|RS2(b)|RD(c));
51 .word (F3F(2, 0x36, 0x131)|RS1(a)|RS2(b)|RD(c));
54 .word (F3F(2, 0x36, 0x134)|RS1(a)|RD(b));
56 .word (F3F(2, 0x36, 0x135)|RS1(a)|RD(b));
[all …]
/arch/sparc/net/
A Dbpf_jit_comp_32.c25 #define RD(X) ((X) << 25) macro
69 (F2(0, 0x4) | RD(REG) | (((K) >> 10) & 0x3fffff))
113 *prog++ = SUB | RS1(G0) | RS2(r_A) | RD(r_A); \
118 *prog++ = OR | RS1(G0) | RS2(FROM) | RD(TO); \
123 *prog++ = OR | RS1(G0) | RS2(G0) | RD(REG); \
161 _insn |= RS1(r_A) | RD(r_A); \
262 *prog++ = (SUBCC | RS1(R1) | RS2(R2) | RD(G0))
268 *prog++ = (ANDCC | RS1(R1) | RS2(R2) | RD(G0))
274 *prog++ = (SUB | RS1(R1) | RS2(R2) | RD(R3))
280 *prog++ = (ADD | RS1(R1) | RS2(R2) | RD(R3))
[all …]
A Dbpf_jit_comp_64.c54 #define RD(X) ((X) << 25) macro
137 (F2(0, 0x4) | RD(REG) | (((K) >> 10) & 0x3fffff))
263 emit(OR | RS1(G0) | RS2(from) | RD(to), ctx); in emit_reg_move()
295 emit(opcode | RS1(a) | RS2(b) | RD(c), ctx); in emit_alu3()
304 insn |= RS1(dst) | RD(dst); in emit_alu_K()
323 insn |= RS1(src) | RD(dst); in emit_alu3_K()
647 emit(SUBCC | RS1(R1) | RS2(R2) | RD(G0), CTX)
653 emit(ANDCC | RS1(R1) | RS2(R2) | RD(G0), CTX)
998 emit(SUB | RS1(0) | RS2(dst) | RD(dst), ctx); in build_insn()
1285 emit(opcode | RS1(src) | rs2 | RD(dst), ctx); in build_insn()
[all …]
/arch/sparc/kernel/
A Dvisemul.c350 store_reg(regs, rd_val, RD(insn)); in edge()
403 store_reg(regs, rd_val, RD(insn)); in array()
415 store_reg(regs, rd_val, RD(insn)); in bmask()
445 *fpd_regaddr(f, RD(insn)) = rd_val; in bshuffle()
456 rd = fpd_regaddr(f, RD(insn)); in pdist()
503 *fps_regaddr(f, RD(insn)) = rd_val; in pformat()
526 *fpd_regaddr(f, RD(insn)) = rd_val; in pformat()
549 *fps_regaddr(f, RD(insn)) = rd_val; in pformat()
567 *fpd_regaddr(f, RD(insn)) = rd_val; in pformat()
583 *fpd_regaddr(f, RD(insn)) = rd_val; in pformat()
[all …]
/arch/arm64/boot/dts/marvell/
A Dac5x-rd-carrier-cn9131.dts5 * Device tree for the AC5X RD Type 7 Com Express carrier board,
11 * AC5X RD works here in external mode (switch selectable at the back of the
17 * the AC5X RD becomes part of the carrier solution.
26 * And it accesses the switch end-point on the AC5X RD portion of the carrier
34 model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board with CN9131 CPU module";
A Dac5x-rd-carrier.dtsi5 * Device tree for the AC5X RD Type 7 Com Express carrier board,
10 * AC5X RD can either work as you would expect, as a complete standalone
17 * the AC5X RD becomes part of the carrier solution.
31 model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board";
A Dac5-98dx35xx-rd.dts3 * Device Tree For RD-AC5X.
18 model = "Marvell RD-AC5X Board";
/arch/arm/boot/dts/marvell/
A Darmada-382-rd-ac3x-48g4x2xl.dts4 * (RD-AC3X-48G4X2XL)
15 model = "Marvell Armada 382 RD-AC3X";
A Darmada-xp-axpwifiap.dts3 * Device Tree file for Marvell RD-AXPWiFiAP.
21 model = "Marvell RD-AXPWiFiAP";
A Darmada-388-rd.dts4 * (RD-88F6820-AP)
A Darmada-370-rd.dts4 * (RD-88F6710-A1)
A Darmada-388-gp.dts4 * (RD-88F6820-GP)
/arch/sh/include/mach-ecovec24/mach/
A Dpartner-jet-setup.txt9 LIST "> RD zImage, 0xa8800000"
14 LIST "> RD romImage, 0"
/arch/riscv/include/asm/
A Dinsn-def.h196 RD(dest), RS1(addr), __RS2(3))
200 RD(dest), RS1(addr), __RS2(0))
205 RD(dest), RS1(addr), __RS2(0))
/arch/sh/include/mach-kfr2r09/mach/
A Dpartner-jet-setup.txt8 LIST "> RD zImage, 0xa8800000"
13 LIST "> RD romImage, 0"
/arch/mips/kernel/
A Dtraps.c512 #define RD 0x0000f800 macro
675 int rd = (opcode & RD) >> 11; in simulate_rdhwr_normal()
731 int rd = (opcode & RD) >> 11; in simulate_loongson3_cpucfg()

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