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Searched refs:REG (Results 1 – 25 of 31) sorted by relevance

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/arch/m68k/lib/
A Dmulsi3.S67 #define d0 REG (d0)
68 #define d1 REG (d1)
69 #define d2 REG (d2)
70 #define d3 REG (d3)
71 #define d4 REG (d4)
72 #define d5 REG (d5)
73 #define d6 REG (d6)
74 #define d7 REG (d7)
75 #define a0 REG (a0)
76 #define a1 REG (a1)
[all …]
A Dumodsi3.S67 #define d0 REG (d0)
68 #define d1 REG (d1)
69 #define d2 REG (d2)
70 #define d3 REG (d3)
71 #define d4 REG (d4)
72 #define d5 REG (d5)
73 #define d6 REG (d6)
74 #define d7 REG (d7)
75 #define a0 REG (a0)
76 #define a1 REG (a1)
[all …]
A Dmodsi3.S69 #define d0 REG (d0)
70 #define d1 REG (d1)
71 #define d2 REG (d2)
72 #define d3 REG (d3)
73 #define d4 REG (d4)
74 #define d5 REG (d5)
75 #define d6 REG (d6)
76 #define d7 REG (d7)
77 #define a0 REG (a0)
78 #define a1 REG (a1)
[all …]
A Ddivsi3.S69 #define d0 REG (d0)
70 #define d1 REG (d1)
71 #define d2 REG (d2)
72 #define d3 REG (d3)
73 #define d4 REG (d4)
74 #define d5 REG (d5)
75 #define d6 REG (d6)
76 #define d7 REG (d7)
77 #define a0 REG (a0)
78 #define a1 REG (a1)
[all …]
A Dudivsi3.S67 #define d0 REG (d0)
68 #define d1 REG (d1)
69 #define d2 REG (d2)
70 #define d3 REG (d3)
71 #define d4 REG (d4)
72 #define d5 REG (d5)
73 #define d6 REG (d6)
74 #define d7 REG (d7)
75 #define a0 REG (a0)
76 #define a1 REG (a1)
[all …]
/arch/sparc/include/asm/
A Dasm.h14 #define BRANCH_REG_ZERO(PREDICT, REG, DEST) \ argument
15 brz,PREDICT REG, DEST
17 brz,a,PREDICT REG, DEST
18 #define BRANCH_REG_NOT_ZERO(PREDICT, REG, DEST) \ argument
19 brnz,PREDICT REG, DEST
21 brnz,a,PREDICT REG, DEST
27 #define BRANCH_REG_ZERO(PREDICT, REG, DEST) \ argument
28 cmp REG, 0; \
31 cmp REG, 0; \
34 cmp REG, 0; \
[all …]
A Dtrap_block.h120 #define __GET_CPUID(REG) \ argument
123 srlx REG, 17, REG; \
124 and REG, 0x1f, REG; \
131 srlx REG, 17, REG; \
132 and REG, 0x3ff, REG; \
136 srlx REG, 17, REG; \
137 and REG, 0x1f, REG; \
141 sllx REG, 9, REG; \
142 or REG, 0xd0, REG; \
143 lduwa [REG] ASI_PHYS_BYPASS_EC_E, REG;\
[all …]
A Dtsb.h77 #define TSB_LOAD_QUAD(TSB, REG) \ argument
78 661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
81 ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \
82 ldda [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \
85 #define TSB_LOAD_TAG_HIGH(TSB, REG) \ argument
86 661: lduwa [TSB] ASI_N, REG; \
89 lduwa [TSB] ASI_PHYS_USE_EC, REG; \
92 #define TSB_LOAD_TAG(TSB, REG) \ argument
93 661: ldxa [TSB] ASI_N, REG; \
96 ldxa [TSB] ASI_PHYS_USE_EC, REG; \
/arch/loongarch/kernel/
A Dhw_breakpoint.c47 READ_WB_REG_CASE(OFF, 0, REG, T, VAL); \
48 READ_WB_REG_CASE(OFF, 1, REG, T, VAL); \
49 READ_WB_REG_CASE(OFF, 2, REG, T, VAL); \
50 READ_WB_REG_CASE(OFF, 3, REG, T, VAL); \
51 READ_WB_REG_CASE(OFF, 4, REG, T, VAL); \
52 READ_WB_REG_CASE(OFF, 5, REG, T, VAL); \
53 READ_WB_REG_CASE(OFF, 6, REG, T, VAL); \
54 READ_WB_REG_CASE(OFF, 7, REG, T, VAL); \
55 READ_WB_REG_CASE(OFF, 8, REG, T, VAL); \
56 READ_WB_REG_CASE(OFF, 9, REG, T, VAL); \
[all …]
/arch/arm64/kernel/
A Dhw_breakpoint.c63 AARCH64_DBG_READ(N, REG, VAL); \
68 AARCH64_DBG_WRITE(N, REG, VAL); \
72 READ_WB_REG_CASE(OFF, 0, REG, VAL); \
73 READ_WB_REG_CASE(OFF, 1, REG, VAL); \
74 READ_WB_REG_CASE(OFF, 2, REG, VAL); \
75 READ_WB_REG_CASE(OFF, 3, REG, VAL); \
76 READ_WB_REG_CASE(OFF, 4, REG, VAL); \
77 READ_WB_REG_CASE(OFF, 5, REG, VAL); \
78 READ_WB_REG_CASE(OFF, 6, REG, VAL); \
87 READ_WB_REG_CASE(OFF, 15, REG, VAL)
[all …]
/arch/loongarch/include/uapi/asm/
A Dkvm.h92 #define LOONGARCH_REG_64(TYPE, REG) (TYPE | KVM_REG_SIZE_U64 | (REG << LOONGARCH_REG_SHIFT)) argument
93 #define KVM_IOC_CSRID(REG) LOONGARCH_REG_64(KVM_REG_LOONGARCH_CSR, REG) argument
94 #define KVM_IOC_CPUCFG(REG) LOONGARCH_REG_64(KVM_REG_LOONGARCH_CPUCFG, REG) argument
/arch/loongarch/include/asm/
A Dhw_breakpoint.h57 #define LOONGARCH_CSR_WATCH_READ(N, REG, T, VAL) \ argument
60 VAL = csr_read64(LOONGARCH_CSR_##IB##N##REG); \
62 VAL = csr_read64(LOONGARCH_CSR_##DB##N##REG); \
65 #define LOONGARCH_CSR_WATCH_WRITE(N, REG, T, VAL) \ argument
68 csr_write64(VAL, LOONGARCH_CSR_##IB##N##REG); \
70 csr_write64(VAL, LOONGARCH_CSR_##DB##N##REG); \
/arch/arm64/include/asm/
A Dhw_breakpoint.h98 #define AARCH64_DBG_READ(N, REG, VAL) do {\ argument
99 VAL = read_sysreg(dbg##REG##N##_el1);\
102 #define AARCH64_DBG_WRITE(N, REG, VAL) do {\ argument
103 write_sysreg(VAL, dbg##REG##N##_el1);\
/arch/sparc/net/
A Dbpf_jit_comp_32.c68 #define SETHI(K, REG) \ argument
70 #define OR_LO(K, REG) \ argument
71 (F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG))
121 #define emit_clear(REG) \ argument
126 #define emit_set_const(K, REG) \ argument
128 *prog++ = SETHI(K, REG); \
130 *prog++ = OR_LO(K, REG); \
220 #define emit_load_cpu(REG) \ argument
223 #define emit_load_cpu(REG) emit_clear(REG) argument
258 #define emit_read_y(REG) *prog++ = RD_Y | RD(REG) argument
[all …]
A Dbpf_jit_comp_64.c136 #define SETHI(K, REG) \ argument
137 (F2(0, 0x4) | RD(REG) | (((K) >> 10) & 0x3fffff))
138 #define OR_LO(K, REG) \ argument
139 (F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG))
643 #define emit_read_y(REG, CTX) emit(RD_Y | RD(REG), CTX) argument
644 #define emit_write_y(REG, CTX) emit(WR_Y | IMMED | RS1(REG) | S13(0), CTX) argument
/arch/sparc/kernel/
A Dpsycho_common.h15 #define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \ argument
18 ((unsigned long)(REG)))
A Dprom_irqtrans.c103 #define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG) \ argument
106 ((unsigned long)(REG)))
/arch/arm64/kvm/hyp/nvhe/
A Dsys_regs.c342 #define AARCH32(REG) { SYS_DESC(REG), .access = pvm_access_id_aarch32 } argument
345 #define AARCH64(REG) { SYS_DESC(REG), .access = pvm_access_id_aarch64 } argument
358 #define RAZ_WI(REG) { SYS_DESC(REG), .access = pvm_access_raz_wi } argument
361 #define HOST_HANDLED(REG) { SYS_DESC(REG), .access = NULL } argument
/arch/powerpc/mm/ptdump/
A Dptdump.c173 #define REG "0x%016lx" in dump_addr() macro
175 #define REG "0x%08lx" in dump_addr()
178 pt_dump_seq_printf(st->seq, REG "-" REG " ", st->start_address, addr - 1); in dump_addr()
179 pt_dump_seq_printf(st->seq, " " REG " ", st->start_pa); in dump_addr()
/arch/mips/kvm/
A Dtrace.h143 #define KVM_TRACE_COP0(REG, SEL) ((KVM_TRACE_HWR_COP0 << 8) | \ argument
144 ((REG) << 3) | (SEL))
145 #define KVM_TRACE_HWR(REG, SEL) ((KVM_TRACE_HWR_HWR << 8) | \ argument
146 ((REG) << 3) | (SEL))
/arch/powerpc/xmon/
A Dxmon.c199 #define REG "%.16lx" macro
201 #define REG "%.8lx" macro
1911 printf("ctr = "REG" xer = "REG" trap = %4lx\n", in prregs()
2159 printf("msr = "REG" sprg0 = "REG"\n", in super_regs()
2161 printf("pvr = "REG" sprg1 = "REG"\n", in super_regs()
2163 printf("dec = "REG" sprg2 = "REG"\n", in super_regs()
2165 printf("sp = "REG" sprg3 = "REG"\n", sp, mfspr(SPRN_SPRG3)); in super_regs()
2166 printf("toc = "REG" dar = "REG"\n", toc, mfspr(SPRN_DAR)); in super_regs()
2847 printf(REG, addr); in dump_by_size()
2966 printf(REG, adrs); in prdump()
[all …]
/arch/powerpc/kernel/
A Dprocess.c1550 #define REG "%016lx" macro
1553 #define REG "%08lx" macro
1561 printk("NIP: "REG" LR: "REG" CTR: "REG"\n", in __show_regs()
1565 printk("MSR: "REG" ", regs->msr); in __show_regs()
1570 pr_cont("CFAR: "REG" ", regs->orig_gpr3); in __show_regs()
1575 pr_cont("DEAR: "REG" ESR: "REG" ", regs->dear, regs->esr); in __show_regs()
1577 pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); in __show_regs()
1591 pr_cont(REG " ", regs->gpr[i]); in __show_regs()
1599 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); in __show_regs()
1600 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); in __show_regs()
[all …]
/arch/arm/boot/dts/nxp/imx/
A Dimx6ull-dhcor-maveo-box.dts79 "", "", "BT-REG-ON", "",
125 "NFC-IRQ", "WL-REG-ON", "DHCOR-BOOT-M0", "DHCOR-BOOT-M1",
/arch/powerpc/include/asm/
A Dreg.h1240 #define MTFSF_L(REG) \ argument
1241 .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
1243 #define MTFSF_L(REG) mtfsf 0xff, (REG) argument
/arch/arm/boot/dts/ti/omap/
A Dam5729-beagleboneai.dts193 reset-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>, /* BT-REG-ON */
194 <&gpio3 18 GPIO_ACTIVE_LOW>; /* WL-REG-ON */

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