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Searched refs:REG2 (Results 1 – 11 of 11) sorted by relevance

/arch/sparc/include/asm/
A Dtsb.h161 andn REG2, 0x7, REG2; \
166 andn REG2, 0x7, REG2; \
171 sllx REG2, 32, REG2; \
175 sllx REG2, 1, REG2; \
178 andn REG2, 0x7, REG2; \
182 sllx REG2, 32, REG2; \
188 and VADDR, REG2, REG2; \
193 andn REG2, 0x7, REG2; \
221 sllx REG2, 1, REG2; \
350 sllx REG2, 4, REG2; \
[all …]
A Dtrap_block.h184 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) \ argument
186 sethi %hi(trap_block), REG2; \
188 or REG2, %lo(trap_block), REG2; \
189 add REG2, REG1, REG2; \
190 ldx [REG2 + TRAP_PER_CPU_PER_CPU_BASE], DEST;
213 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) argument
/arch/arm64/boot/dts/rockchip/
A Drk3368-evb-act8846.dts61 vcc_io: REG2 {
/arch/arm/boot/dts/rockchip/
A Drk3288-evb-act8846.dts92 vcc_io: REG2 {
A Drk3288-firefly-reload-core.dtsi119 vcc_io: REG2 {
A Drk3288-rock2-som.dtsi105 vcc_io: vccio_codec: REG2 {
A Drk3188-radxarock.dts207 vdd_log: REG2 {
A Drk3288-r89.dts186 vcc_io: REG2 {
A Drk3288-miqi.dts193 vcc_io: REG2 {
A Drk3288-firefly.dtsi270 vcc_io: REG2 {
A Drk3188-bqedison2qc.dts325 vdd_log: REG2 {

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