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Searched refs:REG_L (Results 1 – 25 of 31) sorted by relevance

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/arch/riscv/include/asm/
A Dassembler.h23 REG_L t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0)
37 REG_L ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0)
38 REG_L sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0)
39 REG_L gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0)
40 REG_L tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0)
41 REG_L s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0)
42 REG_L s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0)
43 REG_L a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0)
44 REG_L a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0)
71 REG_L t0, 0(a1)
[all …]
A Dasm.h98 REG_L \tmp, 0(\dst)
110 REG_L \dst, 0(\dst)
159 REG_L x6, PT_T1(sp)
160 REG_L x7, PT_T2(sp)
161 REG_L x8, PT_S0(sp)
162 REG_L x9, PT_S1(sp)
163 REG_L x10, PT_A0(sp)
164 REG_L x11, PT_A1(sp)
165 REG_L x12, PT_A2(sp)
166 REG_L x13, PT_A3(sp)
[all …]
A Dword-at-a-time.h65 "1: " REG_L " %0, %2\n" in load_unaligned_zeropad()
A Dscs.h23 REG_L gp, TASK_TI_SCS_SP(tp)
/arch/riscv/kernel/probes/
A Drethook_trampoline.S47 REG_L x3, PT_GP(sp)
48 REG_L x4, PT_TP(sp)
49 REG_L x5, PT_T0(sp)
50 REG_L x6, PT_T1(sp)
51 REG_L x7, PT_T2(sp)
52 REG_L x8, PT_S0(sp)
53 REG_L x9, PT_S1(sp)
54 REG_L x10, PT_A0(sp)
55 REG_L x11, PT_A1(sp)
56 REG_L x12, PT_A2(sp)
[all …]
/arch/riscv/kernel/
A Dmcount-dyn.S44 REG_L a0, ABI_A0(sp)
45 REG_L a1, ABI_A1(sp)
46 REG_L a2, ABI_A2(sp)
47 REG_L a3, ABI_A3(sp)
48 REG_L a4, ABI_A4(sp)
49 REG_L a5, ABI_A5(sp)
50 REG_L a6, ABI_A6(sp)
51 REG_L a7, ABI_A7(sp)
52 REG_L t0, ABI_T0(sp)
53 REG_L ra, ABI_RA(sp)
[all …]
A Dentry.S70 REG_L a2, 0(a0)
80 REG_L a0, TASK_TI_A0(tp)
81 REG_L a1, TASK_TI_A1(tp)
82 REG_L a2, TASK_TI_A2(tp)
196 REG_L t1, 0(t0)
262 REG_L a2, PT_EPC(sp)
268 REG_L x1, PT_RA(sp)
269 REG_L x3, PT_GP(sp)
270 REG_L x4, PT_TP(sp)
271 REG_L x5, PT_T0(sp)
[all …]
A Dmcount.S38 REG_L ra, 1*SZREG(sp)
39 REG_L s0, 0*SZREG(sp)
44 REG_L ra, FREGS_RA(sp)
45 REG_L s0, FREGS_S0(sp)
46 REG_L a0, FREGS_A0(sp)
47 REG_L a1, FREGS_A1(sp)
87 REG_L t1, 0(t0)
91 REG_L t2, 0(t3)
96 REG_L t5, 0(t3)
109 REG_L a2, -2*SZREG(s0)
[all …]
A Dhibernate-asm.S29 REG_L a0, hibernate_cpu_context
49 REG_L s4, restore_pblist
50 REG_L a1, relocated_restore_code
67 REG_L a1, HIBERN_PBE_ADDR(s4)
68 REG_L a0, HIBERN_PBE_ORIG(s4)
72 REG_L s4, HIBERN_PBE_NEXT(s4)
A Dcopy-unaligned.S17 REG_L a4, 0(a1)
18 REG_L a5, SZREG(a1)
19 REG_L a6, 2*SZREG(a1)
20 REG_L a7, 3*SZREG(a1)
21 REG_L t0, 4*SZREG(a1)
22 REG_L t1, 5*SZREG(a1)
23 REG_L t2, 6*SZREG(a1)
24 REG_L t3, 7*SZREG(a1)
A Dhead.S78 REG_L a1, KERNEL_MAP_VIRT_ADDR(a1)
92 REG_L a1, 0(a1)
158 REG_L tp, (a2)
162 REG_L sp, (a3)
362 REG_L sp, (a1)
363 REG_L tp, (a2)
A Dkexec_relocate.S59 REG_L t0, 0(s0) /* t0 = *image->entry */
92 REG_L t1, (t0) /* t1 = *src_ptr */
/arch/riscv/kvm/
A Dvcpu_switch.S67 REG_L ra, (KVM_ARCH_GUEST_RA)(a0)
68 REG_L sp, (KVM_ARCH_GUEST_SP)(a0)
69 REG_L gp, (KVM_ARCH_GUEST_GP)(a0)
70 REG_L tp, (KVM_ARCH_GUEST_TP)(a0)
71 REG_L t0, (KVM_ARCH_GUEST_T0)(a0)
72 REG_L t1, (KVM_ARCH_GUEST_T1)(a0)
73 REG_L t2, (KVM_ARCH_GUEST_T2)(a0)
74 REG_L s0, (KVM_ARCH_GUEST_S0)(a0)
75 REG_L s1, (KVM_ARCH_GUEST_S1)(a0)
76 REG_L a1, (KVM_ARCH_GUEST_A1)(a0)
[all …]
/arch/riscv/lib/
A Dmemcpy.S43 REG_L a4, 0(a1)
44 REG_L a5, SZREG(a1)
45 REG_L a6, 2*SZREG(a1)
46 REG_L a7, 3*SZREG(a1)
47 REG_L t0, 4*SZREG(a1)
48 REG_L t1, 5*SZREG(a1)
49 REG_L t2, 6*SZREG(a1)
50 REG_L t3, 7*SZREG(a1)
51 REG_L t4, 8*SZREG(a1)
52 REG_L t5, 9*SZREG(a1)
[all …]
A Duaccess.S18 REG_L t0, riscv_v_usercopy_threshold
46 REG_L t0, riscv_v_usercopy_threshold
117 fixup REG_L a4, 0(a1), 10f
118 fixup REG_L a5, SZREG(a1), 10f
119 fixup REG_L a6, 2*SZREG(a1), 10f
120 fixup REG_L a7, 3*SZREG(a1), 10f
121 fixup REG_L t1, 4*SZREG(a1), 10f
122 fixup REG_L t2, 5*SZREG(a1), 10f
123 fixup REG_L t3, 6*SZREG(a1), 10f
170 fixup REG_L a5, 0(a1), 10f
[all …]
A Dmemmove.S132 REG_L t0, (0 * SZREG)(a1)
134 REG_L t1, (1 * SZREG)(a1)
143 REG_L t0, (2 * SZREG)(a1)
194 REG_L t1, ( 0 * SZREG)(a4)
196 REG_L t0, (-1 * SZREG)(a4)
205 REG_L t1, (-2 * SZREG)(a4)
231 REG_L t1, ( 0 * SZREG)(a1)
243 REG_L t1, (-1 * SZREG)(a4)
A Dstrcmp.S73 REG_L t0, 0(a0)
74 REG_L t1, 0(a1)
A Dstrlen.S73 REG_L t1, 0(t0)
111 REG_L t1, SZREG(t0)
A Dstrncmp.S82 REG_L t0, 0(a0)
83 REG_L t1, 0(a1)
/arch/mips/fw/lib/
A Dcall_o32.S88 REG_L sp,O32_NFRAMESZ-1*SZREG(sp)
90 REG_L s0,O32_FRAMESZ-11*SZREG(sp)
92 REG_L s2,O32_FRAMESZ-9*SZREG(sp)
93 REG_L s3,O32_FRAMESZ-8*SZREG(sp)
94 REG_L s4,O32_FRAMESZ-7*SZREG(sp)
95 REG_L s5,O32_FRAMESZ-6*SZREG(sp)
96 REG_L s6,O32_FRAMESZ-5*SZREG(sp)
97 REG_L s7,O32_FRAMESZ-4*SZREG(sp)
98 REG_L gp,O32_FRAMESZ-3*SZREG(sp)
99 REG_L fp,O32_FRAMESZ-2*SZREG(sp)
[all …]
/arch/riscv/kernel/vdso/
A Dvgetrandom-chacha.S234 REG_L s0, (sp)
235 REG_L s1, SZREG(sp)
236 REG_L s2, 2*SZREG(sp)
237 REG_L s3, 3*SZREG(sp)
238 REG_L s4, 4*SZREG(sp)
239 REG_L s5, 5*SZREG(sp)
240 REG_L s6, 6*SZREG(sp)
241 REG_L s7, 7*SZREG(sp)
242 REG_L s8, 8*SZREG(sp)
243 REG_L s9, 9*SZREG(sp)
[all …]
/arch/loongarch/vdso/
A Dvgetrandom-chacha.S240 REG_L s0, sp, 0
241 REG_L s1, sp, SZREG
242 REG_L s2, sp, SZREG * 2
243 REG_L s3, sp, SZREG * 3
244 REG_L s4, sp, SZREG * 4
245 REG_L s5, sp, SZREG * 5
246 REG_L s6, sp, SZREG * 6
247 REG_L s7, sp, SZREG * 7
248 REG_L s8, sp, SZREG * 8
249 REG_L s9, sp, SZREG * 9
/arch/riscv/errata/sifive/
A Derrata_cip_453.S12 REG_L \badaddr, PT_BADADDR(\pt_reg)
/arch/loongarch/include/asm/
A Dasm.h55 #define REG_L ld.w macro
60 #define REG_L ld.d macro
/arch/mips/include/asm/
A Dasm.h159 #define REG_L lw macro
165 #define REG_L ld macro

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