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Searched refs:RV_X (Results 1 – 4 of 4) sorted by relevance

/arch/riscv/kernel/
A Dmachine_kexec_file.c120 (RV_X(x, 0, 12) << 20)
122 ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | \
123 (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31))
125 (RV_X(x, 12, 20) << 12)
127 ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | \
128 (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))
130 ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | \
131 (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
133 ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | \
134 (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | \
[all …]
A Dtraps_misaligned.c117 #define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \
118 (RV_X(x, 10, 3) << 3) | \
119 (RV_X(x, 5, 1) << 6))
121 (RV_X(x, 5, 2) << 6))
123 (RV_X(x, 12, 1) << 5) | \
124 (RV_X(x, 2, 2) << 6))
126 (RV_X(x, 12, 1) << 5) | \
127 (RV_X(x, 2, 3) << 6))
129 (RV_X(x, 7, 2) << 6))
131 (RV_X(x, 7, 3) << 6))
[all …]
/arch/riscv/include/asm/
A Dinsn.h291 #define RV_X(X, s, mask) (((X) >> (s)) & (mask)) macro
292 #define RVC_X(X, s, mask) RV_X(X, s, mask)
296 (RV_X(x_, RVG_RS1_OPOFF, RVG_RS1_MASK)); })
300 (RV_X(x_, RVG_RD_OPOFF, RVG_RD_MASK)); })
304 (RV_X(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); })
309 (RV_X(x_, RV_J_IMM_11_OPOFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OFF) | \
315 (RV_X(x_, RV_I_IMM_11_0_OPOFF, RV_I_IMM_11_0_MASK)) | \
322 (RV_X(x_, RV_B_IMM_11_OPOFF, RV_B_IMM_11_MASK) << RV_B_IMM_11_OFF) | \
327 (RV_X(x_, RVC_C2_RS1_OPOFF, RVC_C2_RS1_MASK)); })
352 ({typeof(x) x_ = (x); RV_X(x_, RVFDQ_FL_FS_WIDTH_OFF, \
[all …]
/arch/riscv/kvm/
A Dvcpu_insn.c95 #define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \
96 (RV_X(x, 10, 3) << 3) | \
97 (RV_X(x, 5, 1) << 6))
99 (RV_X(x, 5, 2) << 6))
101 (RV_X(x, 12, 1) << 5) | \
102 (RV_X(x, 2, 2) << 6))
104 (RV_X(x, 12, 1) << 5) | \
105 (RV_X(x, 2, 3) << 6))
107 (RV_X(x, 7, 2) << 6))
109 (RV_X(x, 7, 3) << 6))
[all …]

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