Searched refs:SH_RD (Results 1 – 2 of 2) sorted by relevance
| /arch/riscv/kernel/ |
| A D | traps_misaligned.c | 111 #define SH_RD 7 macro
132 #define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3))
154 #define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val))
410 insn = RVC_RS2S(insn) << SH_RD; in handle_scalar_misaligned_load()
412 ((insn >> SH_RD) & 0x1f)) { in handle_scalar_misaligned_load()
419 insn = RVC_RS2S(insn) << SH_RD; in handle_scalar_misaligned_load()
421 ((insn >> SH_RD) & 0x1f)) { in handle_scalar_misaligned_load()
427 insn = RVC_RS2S(insn) << SH_RD; in handle_scalar_misaligned_load()
435 insn = RVC_RS2S(insn) << SH_RD; in handle_scalar_misaligned_load()
442 insn = RVC_RS2S(insn) << SH_RD; in handle_scalar_misaligned_load()
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| /arch/riscv/kvm/ |
| A D | vcpu_insn.c | 88 #define SH_RD 7 macro
110 #define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3))
134 #define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val))
263 if ((insn >> SH_RD) & MASK_RX) in kvm_riscv_vcpu_csr_return()
541 insn = RVC_RS2S(insn) << SH_RD; in kvm_riscv_vcpu_mmio_load()
543 ((insn >> SH_RD) & 0x1f)) { in kvm_riscv_vcpu_mmio_load()
550 insn = RVC_RS2S(insn) << SH_RD; in kvm_riscv_vcpu_mmio_load()
552 ((insn >> SH_RD) & 0x1f)) { in kvm_riscv_vcpu_mmio_load()
659 ((insn >> SH_RD) & 0x1f)) { in kvm_riscv_vcpu_mmio_store()
667 ((insn >> SH_RD) & 0x1f)) { in kvm_riscv_vcpu_mmio_store()
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