| /arch/powerpc/lib/ |
| A D | feature-fixups-test.S | 231 BEGIN_##TYPE##_SECTION \
239 BEGIN_##TYPE##_SECTION \
247 BEGIN_##TYPE##_SECTION \
260 BEGIN_##TYPE##_SECTION \
273 BEGIN_##TYPE##_SECTION \
290 ##TYPE##_SECTION_ELSE \
301 ##TYPE##_SECTION_ELSE \
313 ##TYPE##_SECTION_ELSE \
327 ##TYPE##_SECTION_ELSE \
338 ##TYPE##_SECTION_ELSE \
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| /arch/sparc/math-emu/ |
| A D | math_32.c | 302 case FDIVQ: TYPE(3,3,1,3,1,3,1); break; in do_one_mathemu()
304 case FQTOS: TYPE(3,1,1,3,1,0,0); break; in do_one_mathemu()
305 case FQTOD: TYPE(3,2,1,3,1,0,0); break; in do_one_mathemu()
306 case FITOQ: TYPE(3,3,1,1,0,0,0); break; in do_one_mathemu()
307 case FSTOQ: TYPE(3,3,1,1,1,0,0); break; in do_one_mathemu()
308 case FDTOQ: TYPE(3,3,1,2,1,0,0); break; in do_one_mathemu()
309 case FQTOI: TYPE(3,1,0,3,1,0,0); break; in do_one_mathemu()
315 case FDIVD: TYPE(2,2,1,2,1,2,1); break; in do_one_mathemu()
319 case FDIVS: TYPE(2,1,1,1,1,1,1); break; in do_one_mathemu()
321 case FDTOS: TYPE(2,1,1,2,1,0,0); break; in do_one_mathemu()
[all …]
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| A D | math_64.c | 198 case FABSQ: TYPE(3,3,0,3,0,0,0); break; in do_mathemu()
203 case FDIVQ: TYPE(3,3,1,3,1,3,1); break; in do_mathemu()
205 case FQTOX: TYPE(3,2,0,3,1,0,0); break; in do_mathemu()
206 case FXTOQ: TYPE(3,3,1,2,0,0,0); break; in do_mathemu()
207 case FQTOS: TYPE(3,1,1,3,1,0,0); break; in do_mathemu()
208 case FQTOD: TYPE(3,2,1,3,1,0,0); break; in do_mathemu()
209 case FITOQ: TYPE(3,3,1,1,0,0,0); break; in do_mathemu()
210 case FSTOQ: TYPE(3,3,1,1,1,0,0); break; in do_mathemu()
223 TYPE(x,1,1,1,1,0,0); in do_mathemu()
231 TYPE(x,2,1,2,1,0,0); in do_mathemu()
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| /arch/sparc/include/asm/ |
| A D | asm.h | 10 #define BRANCH32(TYPE, PREDICT, DEST) \ argument
11 TYPE,PREDICT %icc, DEST
12 #define BRANCH32_ANNUL(TYPE, PREDICT, DEST) \ argument
13 TYPE,a,PREDICT %icc, DEST
23 #define BRANCH32(TYPE, PREDICT, DEST) \ argument
24 TYPE DEST
25 #define BRANCH32_ANNUL(TYPE, PREDICT, DEST) \ argument
26 TYPE,a DEST
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| A D | vio.h | 471 #define viodbg(TYPE, f, a...) \ argument
472 do { if (vio->debug & VIO_DEBUG_##TYPE) \
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| /arch/mips/include/asm/octeon/ |
| A D | cvmx.h | 212 #define CVMX_BUILD_WRITE64(TYPE, ST) \ argument
213 static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \
215 *CASTPTR(volatile TYPE##_t, addr) = val; \
226 #define CVMX_BUILD_READ64(TYPE, LT) \ argument
227 static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \
229 return *CASTPTR(volatile TYPE##_t, addr); \
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| /arch/x86/kernel/fpu/ |
| A D | init.c | 146 #define CHECK_MEMBER_AT_END_OF(TYPE, MEMBER) \ argument
147 BUILD_BUG_ON(sizeof(TYPE) != \
148 ALIGN(offsetofend(TYPE, MEMBER), _Alignof(TYPE)))
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| /arch/riscv/include/asm/ |
| A D | vector.h | 25 #define __riscv_v_vstate_or(_val, TYPE) ({ \ argument
28 _res = (_res & ~SR_VS_THEAD) | SR_VS_##TYPE##_THEAD; \
30 _res = (_res & ~SR_VS) | SR_VS_##TYPE; \
34 #define __riscv_v_vstate_check(_val, TYPE) ({ \ argument
37 _res = ((_val) & SR_VS_THEAD) == SR_VS_##TYPE##_THEAD; \
39 _res = ((_val) & SR_VS) == SR_VS_##TYPE; \
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| /arch/alpha/include/asm/ |
| A D | pal.h | 18 #define __CALL_PAL_R0(NAME, TYPE) \ argument
19 extern inline TYPE NAME(void) \
21 register TYPE __r0 __asm__("$0"); \
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| A D | io.h | 134 #define REMAP1(TYPE, NAME, QUAL) \ argument
135 static inline TYPE generic_##NAME(QUAL void __iomem *addr) \
140 #define REMAP2(TYPE, NAME, QUAL) \ argument
141 static inline void generic_##NAME(TYPE b, QUAL void __iomem *addr) \
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| /arch/loongarch/include/uapi/asm/ |
| A D | kvm.h | 92 #define LOONGARCH_REG_64(TYPE, REG) (TYPE | KVM_REG_SIZE_U64 | (REG << LOONGARCH_REG_SHIFT)) argument
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| /arch/arm64/boot/dts/amlogic/ |
| A D | meson-gxm-s912-libretech-pc.dts | 31 * Make sure the irq pin of the TYPE C controller is not driven
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| /arch/arm64/kernel/ |
| A D | cpufeature.c | 190 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ argument
195 .type = TYPE, \
202 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ argument
203 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
206 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ argument
207 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
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| /arch/arm64/boot/dts/mediatek/ |
| A D | mt8395-radxa-nio-12l.dts | 97 /* Rail from power-only "TYPE C DC" port */
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| /arch/sparc/kernel/ |
| A D | ldc.c | 176 #define ldcdbg(TYPE, f, a...) \ argument
177 do { if (lp->cfg.debug & LDC_DEBUG_##TYPE) \
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| /arch/arm/boot/dts/st/ |
| A D | ste-ux500-samsung-codina-tmo.dts | 270 /* TYPE 3: inverse clock polarity and phase */
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| A D | ste-ux500-samsung-gavini.dts | 302 /* TYPE 3: inverse clock polarity and phase */
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| A D | ste-ux500-samsung-janice.dts | 299 /* TYPE 3: inverse clock polarity and phase */
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| A D | ste-ux500-samsung-codina.dts | 362 /* TYPE 3: inverse clock polarity and phase */
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| /arch/arm64/tools/ |
| A D | sysreg | 1345 Enum 13:8 TYPE
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| /arch/m68k/ifpsp060/src/ |
| A D | fpsp.S | 4061 # bftst %d0{&7:&3} # test TYPE
4066 # TYPE == 0: General instructions #
4254 # TYPE == 1: FDB<cc>, FS<cc>, FTRAP<cc>
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