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Searched refs:V7M_SCB_CCSIDR (Results 1 – 3 of 3) sorted by relevance

/arch/arm/include/asm/
A Dv7m.h59 #define V7M_SCB_CCSIDR 0x80 /* Cache size ID register */ macro
A Dcachetype.h105 return readl(BASEADDR_V7M_SCB + V7M_SCB_CCSIDR); in read_ccsidr()
/arch/arm/mm/
A Dcache-v7m.S39 v7m_cache_read \rt, V7M_SCB_CCSIDR

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