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Searched refs:VADDR (Results 1 – 4 of 4) sorted by relevance

/arch/sparc/include/asm/
A Dtsb.h164 sllx VADDR, 64 - (PUD_SHIFT + PUD_BITS), REG2; \
176 sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
188 and VADDR, REG2, REG2; \
191 698: sllx VADDR, 64 - PMD_SHIFT, REG2; \
224 and VADDR, REG2, REG2; \
252 and VADDR, REG2, REG2; \
288 sllx VADDR, 64 - PMD_SHIFT, REG2; \
310 cmp REG2, VADDR; \
312 cmp VADDR, REG3; \
315 sub VADDR, REG2, REG2; \
[all …]
A Dpgtsrmmu.h106 #define __nocache_pa(VADDR) (((unsigned long)VADDR) - SRMMU_NOCACHE_VADDR + __pa((unsigned long)srm… argument
108 #define __nocache_fix(VADDR) ((__typeof__(VADDR))__va(__nocache_pa(VADDR))) argument
/arch/sparc/kernel/
A Dsun4v_tlb_miss.S11 #define LOAD_ITLB_INFO(BASE, VADDR, CTX) \ argument
12 ldx [BASE + HV_FAULT_I_ADDR_OFFSET], VADDR; \
16 #define LOAD_DTLB_INFO(BASE, VADDR, CTX) \ argument
17 ldx [BASE + HV_FAULT_D_ADDR_OFFSET], VADDR; \
24 #define COMPUTE_TAG_TARGET(DEST, VADDR, CTX, ZERO_CTX_LABEL) \ argument
25 srlx VADDR, 22, DEST; \
36 #define COMPUTE_TSB_PTR(TSB_PTR, VADDR, HASH_SHIFT, TMP1, TMP2) \ argument
41 srlx VADDR, HASH_SHIFT, TMP1; \
A Dtrampoline_64.S162 stx %g2, [%sp + 2047 + 128 + 0x28] ! VADDR
195 stx %g2, [%sp + 2047 + 128 + 0x28] ! VADDR

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