| /arch/loongarch/kernel/ |
| A D | hw_breakpoint.c | 47 READ_WB_REG_CASE(OFF, 0, REG, T, VAL); \
48 READ_WB_REG_CASE(OFF, 1, REG, T, VAL); \
49 READ_WB_REG_CASE(OFF, 2, REG, T, VAL); \
50 READ_WB_REG_CASE(OFF, 3, REG, T, VAL); \
51 READ_WB_REG_CASE(OFF, 4, REG, T, VAL); \
52 READ_WB_REG_CASE(OFF, 5, REG, T, VAL); \
53 READ_WB_REG_CASE(OFF, 6, REG, T, VAL); \
54 READ_WB_REG_CASE(OFF, 7, REG, T, VAL); \
55 READ_WB_REG_CASE(OFF, 8, REG, T, VAL); \
56 READ_WB_REG_CASE(OFF, 9, REG, T, VAL); \
[all …]
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| /arch/arm64/include/asm/ |
| A D | rqspinlock.h | 36 __unqual_scalar_typeof(*ptr) VAL; \
39 VAL = READ_ONCE(*__PTR); \
49 (typeof(*ptr))VAL; \
56 __unqual_scalar_typeof(*ptr) VAL; \
58 VAL = smp_load_acquire(__PTR); \
61 __cmpwait_relaxed(__PTR, VAL); \
65 (typeof(*ptr))VAL; \
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| A D | barrier.h | 199 __unqual_scalar_typeof(*ptr) VAL; \
201 VAL = READ_ONCE(*__PTR); \
204 __cmpwait_relaxed(__PTR, VAL); \
206 (typeof(*ptr))VAL; \
212 __unqual_scalar_typeof(*ptr) VAL; \
214 VAL = smp_load_acquire(__PTR); \
217 __cmpwait_relaxed(__PTR, VAL); \
219 (typeof(*ptr))VAL; \
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| A D | hw_breakpoint.h | 98 #define AARCH64_DBG_READ(N, REG, VAL) do {\ argument
99 VAL = read_sysreg(dbg##REG##N##_el1);\
102 #define AARCH64_DBG_WRITE(N, REG, VAL) do {\ argument
103 write_sysreg(VAL, dbg##REG##N##_el1);\
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| A D | mte.h | 93 smp_cond_load_acquire(&page->flags, VAL & (1UL << PG_mte_tagged)); in try_page_mte_tagging()
207 smp_cond_load_acquire(&folio->flags, VAL & (1UL << PG_mte_tagged)); in folio_try_hugetlb_mte_tagging()
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| /arch/arm64/kernel/ |
| A D | hw_breakpoint.c | 63 AARCH64_DBG_READ(N, REG, VAL); \
68 AARCH64_DBG_WRITE(N, REG, VAL); \
72 READ_WB_REG_CASE(OFF, 0, REG, VAL); \
73 READ_WB_REG_CASE(OFF, 1, REG, VAL); \
74 READ_WB_REG_CASE(OFF, 2, REG, VAL); \
75 READ_WB_REG_CASE(OFF, 3, REG, VAL); \
76 READ_WB_REG_CASE(OFF, 4, REG, VAL); \
77 READ_WB_REG_CASE(OFF, 5, REG, VAL); \
78 READ_WB_REG_CASE(OFF, 6, REG, VAL); \
87 READ_WB_REG_CASE(OFF, 15, REG, VAL)
[all …]
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| /arch/arm/kernel/ |
| A D | hw_breakpoint.c | 60 READ_WB_REG_CASE(OP2, 0, VAL); \
61 READ_WB_REG_CASE(OP2, 1, VAL); \
62 READ_WB_REG_CASE(OP2, 2, VAL); \
63 READ_WB_REG_CASE(OP2, 3, VAL); \
64 READ_WB_REG_CASE(OP2, 4, VAL); \
65 READ_WB_REG_CASE(OP2, 5, VAL); \
66 READ_WB_REG_CASE(OP2, 6, VAL); \
67 READ_WB_REG_CASE(OP2, 7, VAL); \
68 READ_WB_REG_CASE(OP2, 8, VAL); \
75 READ_WB_REG_CASE(OP2, 15, VAL)
[all …]
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| /arch/loongarch/include/asm/ |
| A D | hw_breakpoint.h | 57 #define LOONGARCH_CSR_WATCH_READ(N, REG, T, VAL) \ argument
60 VAL = csr_read64(LOONGARCH_CSR_##IB##N##REG); \
62 VAL = csr_read64(LOONGARCH_CSR_##DB##N##REG); \
65 #define LOONGARCH_CSR_WATCH_WRITE(N, REG, T, VAL) \ argument
68 csr_write64(VAL, LOONGARCH_CSR_##IB##N##REG); \
70 csr_write64(VAL, LOONGARCH_CSR_##DB##N##REG); \
|
| /arch/riscv/include/asm/ |
| A D | barrier.h | 72 __unqual_scalar_typeof(*ptr) VAL; \
74 VAL = READ_ONCE(*__PTR); \
77 __cmpwait_relaxed(ptr, VAL); \
79 (typeof(*ptr))VAL; \
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| /arch/arm/include/asm/ |
| A D | hw_breakpoint.h | 110 #define ARM_DBG_READ(N, M, OP2, VAL) do {\ argument
111 asm volatile("mrc p14, 0, %0, " #N "," #M ", " #OP2 : "=r" (VAL));\
114 #define ARM_DBG_WRITE(N, M, OP2, VAL) do {\ argument
115 asm volatile("mcr p14, 0, %0, " #N "," #M ", " #OP2 : : "r" (VAL));\
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| /arch/sparc/include/asm/ |
| A D | tsb.h | 113 #define TSB_STORE(ADDR, VAL) \ argument
114 661: stxa VAL, [ADDR] ASI_N; \
117 stxa VAL, [ADDR] ASI_PHYS_USE_EC; \
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| /arch/x86/kernel/ |
| A D | alternative.c | 2962 atomic_cond_read_acquire(refs, !VAL); in smp_text_poke_batch_finish()
|