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Searched refs:VECSIZE (Results 1 – 5 of 5) sorted by relevance

/arch/loongarch/mm/
A Dtlb.c263 extern long exception_handlers[VECSIZE * 128 / sizeof(long)];
283 set_handler(i * VECSIZE, exception_table[i], VECSIZE); in setup_tlb_handler()
308 csr_write64(pcpu_handlers[cpu] + 80*VECSIZE, LOONGARCH_CSR_TLBRENTRY); in setup_tlb_handler()
/arch/loongarch/kernel/
A Dunwind_prologue.c35 if (entry_offset >= EXCCODE_INT_START * VECSIZE) in scan_handlers()
38 idx = entry_offset / VECSIZE; in scan_handlers()
39 offset = entry_offset % VECSIZE; in scan_handlers()
A Dtraps.c1126 long exception_handlers[VECSIZE * 128 / sizeof(long)] __aligned(SZ_64K);
1131 tlbrentry = (unsigned long)exception_handlers + 80*VECSIZE; in configure_exception_vector()
1142 setup_vint_size(VECSIZE); in per_cpu_trap_init()
1157 set_handler(i * VECSIZE, handle_reserved, VECSIZE); in per_cpu_trap_init()
1194 set_handler(i * VECSIZE, handle_vint, VECSIZE); in trap_init()
1198 set_handler(i * VECSIZE, exception_table[i], VECSIZE); in trap_init()
A Dunwind_orc.c369 if (ra >= eentry && ra < eentry + EXCCODE_INT_END * VECSIZE) { in bt_address()
371 unsigned long type = (ra - eentry) / VECSIZE; in bt_address()
372 unsigned long offset = (ra - eentry) % VECSIZE; in bt_address()
/arch/loongarch/include/asm/
A Dsetup.h13 #define VECSIZE 0x200 macro

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