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Searched refs:X2APIC_MSR (Results 1 – 5 of 5) sorted by relevance

/arch/x86/kvm/svm/
A Dsvm.c742 X2APIC_MSR(APIC_ID), in svm_set_x2apic_msr_interception()
743 X2APIC_MSR(APIC_LVR), in svm_set_x2apic_msr_interception()
747 X2APIC_MSR(APIC_EOI), in svm_set_x2apic_msr_interception()
748 X2APIC_MSR(APIC_RRR), in svm_set_x2apic_msr_interception()
749 X2APIC_MSR(APIC_LDR), in svm_set_x2apic_msr_interception()
750 X2APIC_MSR(APIC_DFR), in svm_set_x2apic_msr_interception()
752 X2APIC_MSR(APIC_ISR), in svm_set_x2apic_msr_interception()
753 X2APIC_MSR(APIC_TMR), in svm_set_x2apic_msr_interception()
754 X2APIC_MSR(APIC_IRR), in svm_set_x2apic_msr_interception()
755 X2APIC_MSR(APIC_ESR), in svm_set_x2apic_msr_interception()
[all …]
/arch/x86/kvm/vmx/
A Dtdx.c2199 case X2APIC_MSR(APIC_TASKPRI): in tdx_has_emulated_msr()
2200 case X2APIC_MSR(APIC_PROCPRI): in tdx_has_emulated_msr()
2201 case X2APIC_MSR(APIC_EOI): in tdx_has_emulated_msr()
2202 case X2APIC_MSR(APIC_ISR) ... X2APIC_MSR(APIC_ISR + APIC_ISR_NR): in tdx_has_emulated_msr()
2203 case X2APIC_MSR(APIC_TMR) ... X2APIC_MSR(APIC_TMR + APIC_ISR_NR): in tdx_has_emulated_msr()
2204 case X2APIC_MSR(APIC_IRR) ... X2APIC_MSR(APIC_IRR + APIC_ISR_NR): in tdx_has_emulated_msr()
A Dvmx.c4043 vmx_set_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW, in vmx_update_msr_bitmap_x2apic()
4047 vmx_enable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_RW); in vmx_update_msr_bitmap_x2apic()
4048 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_EOI), MSR_TYPE_W); in vmx_update_msr_bitmap_x2apic()
4049 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W); in vmx_update_msr_bitmap_x2apic()
4051 vmx_disable_intercept_for_msr(vcpu, X2APIC_MSR(APIC_ICR), MSR_TYPE_RW); in vmx_update_msr_bitmap_x2apic()
A Dnested.c680 X2APIC_MSR(APIC_TASKPRI), in nested_vmx_prepare_msr_bitmap()
686 X2APIC_MSR(APIC_EOI), in nested_vmx_prepare_msr_bitmap()
690 X2APIC_MSR(APIC_SELF_IPI), in nested_vmx_prepare_msr_bitmap()
/arch/x86/kvm/
A Dlapic.h26 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4)) macro

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