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Searched refs:__raw_writeb (Results 1 – 25 of 66) sorted by relevance

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/arch/sh/boards/mach-sh03/
A Drtc.c64 __raw_writeb(0, RTC_SEC1); __raw_writeb(0, RTC_SEC10); in sh03_rtc_gettimeofday()
65 __raw_writeb(0, RTC_MIN1); __raw_writeb(0, RTC_MIN10); in sh03_rtc_gettimeofday()
66 __raw_writeb(0, RTC_HOU1); __raw_writeb(0, RTC_HOU10); in sh03_rtc_gettimeofday()
67 __raw_writeb(6, RTC_WEE1); in sh03_rtc_gettimeofday()
68 __raw_writeb(1, RTC_DAY1); __raw_writeb(0, RTC_DAY10); in sh03_rtc_gettimeofday()
69 __raw_writeb(1, RTC_MON1); __raw_writeb(0, RTC_MON10); in sh03_rtc_gettimeofday()
70 __raw_writeb(0, RTC_YEA1); __raw_writeb(0, RTC_YEA10); in sh03_rtc_gettimeofday()
71 __raw_writeb(0, RTC_YEA100); in sh03_rtc_gettimeofday()
72 __raw_writeb(2, RTC_YEA1000); in sh03_rtc_gettimeofday()
73 __raw_writeb(0, RTC_CTL); in sh03_rtc_gettimeofday()
[all …]
/arch/m68k/coldfire/
A Dintc-simr.c72 __raw_writeb(irq - 128, MCFINTC2_SIMR); in intc_irq_mask()
74 __raw_writeb(irq - 64, MCFINTC1_SIMR); in intc_irq_mask()
76 __raw_writeb(irq, MCFINTC0_SIMR); in intc_irq_mask()
84 __raw_writeb(irq - 128, MCFINTC2_CIMR); in intc_irq_unmask()
86 __raw_writeb(irq - 64, MCFINTC1_CIMR); in intc_irq_unmask()
88 __raw_writeb(irq, MCFINTC0_CIMR); in intc_irq_unmask()
95 __raw_writeb(0x1 << ebit, MCFEPORT_EPFR); in intc_irq_ack()
123 __raw_writeb(5, MCFINTC0_ICR0 + irq); in intc_irq_startup()
182 __raw_writeb(0xff, MCFINTC0_SIMR); in init_IRQ()
184 __raw_writeb(0xff, MCFINTC1_SIMR); in init_IRQ()
[all …]
A Dstmark2.c107 __raw_writeb(0x80, MCFGPIO_PAR_DSPIOWL); in init_stmark2()
108 __raw_writeb(0xfc, MCFGPIO_PAR_DSPIOWH); in init_stmark2()
111 __raw_writeb(0x00, MCFGPIO_PAR_BE); in init_stmark2()
112 __raw_writeb(0x00, MCFGPIO_PAR_FBCTL); in init_stmark2()
113 __raw_writeb(0x00, MCFGPIO_PAR_CS); in init_stmark2()
116 __raw_writeb(0x50, MCFGPIO_PAR_CANI2C); in init_stmark2()
A Dm54xx.c54 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0); in m54xx_uarts_init()
55 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS, in m54xx_uarts_init()
57 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS | in m54xx_uarts_init()
59 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3); in m54xx_uarts_init()
A Dclk.c45 __raw_writeb(clk->slot, MCFPM_PPMCR0); in __clk_enable0()
50 __raw_writeb(clk->slot, MCFPM_PPMSR0); in __clk_disable0()
61 __raw_writeb(clk->slot, MCFPM_PPMCR1); in __clk_enable1()
66 __raw_writeb(clk->slot, MCFPM_PPMSR1); in __clk_disable1()
A Dreset.c30 __raw_writeb(0xc0, MCFSIM_SYPCR); in mcf_cpu_reset()
40 __raw_writeb(MCF_RCR_SWRESET, MCF_RCR); in mcf_cpu_reset()
A Dintc-2.c100 __raw_writeb(0x1 << (irq - EINT0), MCFEPORT_EPFR); in intc_irq_ack()
124 __raw_writeb(intc_intpri--, icraddr); in intc_irq_startup()
134 __raw_writeb(v & ~(0x1 << irq), MCFEPORT_EPDDR); in intc_irq_startup()
138 __raw_writeb(v | (0x1 << irq), MCFEPORT_EPIER); in intc_irq_startup()
A Ddma_timer.c59 __raw_writeb(0x00, DTXMR0); in init_cf_dt_clocksource()
60 __raw_writeb(0x00, DTER0); in init_cf_dt_clocksource()
A Dm5441x.c232 __raw_writeb(0x0f, MCFGPIO_PAR_UART0); in m5441x_uarts_init()
233 __raw_writeb(0x00, MCFGPIO_PAR_UART1); in m5441x_uarts_init()
234 __raw_writeb(0x00, MCFGPIO_PAR_UART2); in m5441x_uarts_init()
239 __raw_writeb(0x03, MCFGPIO_PAR_FEC); in m5441x_fec_init()
A Dtimers.c75 __raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, TA(MCFTIMER_TER)); in mcftmr_tick()
161 __raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, PA(MCFTIMER_TER)); in coldfire_profile_tick()
/arch/sh/boards/mach-hp6xx/
A Dpm.c61 __raw_writeb(stbcr | STBCR_STBY | STBCR_MSTP2, STBCR); in pm_enter()
92 __raw_writeb(stbcr, STBCR); in pm_enter()
117 __raw_writeb(0x1f, DACR); in hp6x0_pm_enter()
120 __raw_writeb(0x01, STBCR); in hp6x0_pm_enter()
123 __raw_writeb(0x7f , STBCR2); in hp6x0_pm_enter()
130 __raw_writeb(stbcr, STBCR); in hp6x0_pm_enter()
131 __raw_writeb(stbcr2, STBCR2); in hp6x0_pm_enter()
/arch/sh/include/cpu-sh3/cpu/
A Ddac.h24 __raw_writeb(v,DACR); in sh_dac_enable()
33 __raw_writeb(v,DACR); in sh_dac_disable()
38 if(channel) __raw_writeb(value,DADR1); in sh_dac_output()
39 else __raw_writeb(value,DADR0); in sh_dac_output()
/arch/arm/boot/compressed/
A Dmisc-ep93xx.h13 static inline void __raw_writeb(unsigned char value, unsigned int ptr) in __raw_writeb() function
51 __raw_writeb(TS72XX_WDT_FEED_VAL, TS72XX_WDT_FEED_PHYS_BASE); in ts72xx_watchdog_disable()
52 __raw_writeb(0, TS72XX_WDT_CONTROL_PHYS_BASE); in ts72xx_watchdog_disable()
/arch/hexagon/include/asm/
A Dio.h83 static inline void __raw_writeb(u8 data, volatile void __iomem *addr) in __raw_writeb() function
92 #define __raw_writeb __raw_writeb macro
/arch/sh/cchips/hd6446x/
A Dhd64461.c49 __raw_writeb(0x00, HD64461_PCC1CSCR); in hd64461_mask_and_ack_irq()
105 __raw_writeb(0x4c, HD64461_PCC1CSCIER); in setup_hd64461()
106 __raw_writeb(0x00, HD64461_PCC1CSCR); in setup_hd64461()
/arch/sh/kernel/cpu/
A Dadc.c24 __raw_writeb(csr, ADCSR); in adc_single()
31 __raw_writeb(csr, ADCSR); in adc_single()
/arch/sh/include/mach-se/mach/
A Dmrshpc.h49 __raw_writeb(0x00, PA_MRSHPC_MW2 + 0x206); in mrshpc_setup_windows()
50 __raw_writeb(0x42, PA_MRSHPC_MW2 + 0x200); in mrshpc_setup_windows()
/arch/sh/include/mach-common/mach/
A Dmagicpanelr2.h19 #define SETBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) | mask, reg)
22 #define CLRBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) & ~mask, reg)
/arch/riscv/include/asm/
A Dmmio.h19 #define __raw_writeb __raw_writeb macro
20 static inline void __raw_writeb(u8 val, volatile void __iomem *addr) in __raw_writeb() function
92 #define writeb_cpu(v, c) ((void)__raw_writeb((v), (c)))
/arch/sh/boards/mach-landisk/
A Dsetup.c23 __raw_writeb(0x01, PA_SHUTDOWN); in landisk_power_off()
89 __raw_writeb(__raw_readb(PA_LED) | 0x03, PA_LED); in landisk_setup()
/arch/arc/include/asm/
A Dio.h123 #define __raw_writeb __raw_writeb macro
124 static inline void __raw_writeb(u8 b, volatile void __iomem *addr) in __raw_writeb() function
225 #define writeb_relaxed(v,c) __raw_writeb(v,c)
/arch/sh/kernel/cpu/sh4a/
A Dsetup-sh7724.c1244 __raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080); /* IMR0 */ in sh7724_post_sleep_notifier_call()
1245 __raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084); /* IMR1 */ in sh7724_post_sleep_notifier_call()
1246 __raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088); /* IMR2 */ in sh7724_post_sleep_notifier_call()
1247 __raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c); /* IMR3 */ in sh7724_post_sleep_notifier_call()
1248 __raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090); /* IMR4 */ in sh7724_post_sleep_notifier_call()
1249 __raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094); /* IMR5 */ in sh7724_post_sleep_notifier_call()
1250 __raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098); /* IMR6 */ in sh7724_post_sleep_notifier_call()
1251 __raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c); /* IMR7 */ in sh7724_post_sleep_notifier_call()
1252 __raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0); /* IMR8 */ in sh7724_post_sleep_notifier_call()
1253 __raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4); /* IMR9 */ in sh7724_post_sleep_notifier_call()
[all …]
/arch/sh/boards/
A Dboard-magicpanelr2.c163 __raw_writeb(0x30, PORT_PMDR); in setup_port_multiplexing()
165 __raw_writeb(0xF0, PORT_PMDR); in setup_port_multiplexing()
175 __raw_writeb(0x10, PORT_PPDR); in setup_port_multiplexing()
/arch/m68k/include/asm/
A Dio_no.h23 #define __raw_writeb(b, addr) (void)((*(__force volatile u8 *) (addr)) = (b)) macro
104 #define writeb __raw_writeb
/arch/arm/include/asm/
A Dio.h85 #define __raw_writeb __raw_writeb macro
86 static inline void __raw_writeb(u8 val, volatile void __iomem *addr) in __raw_writeb() function
235 #define outb(v,p) ({ __iowmb(); __raw_writeb(v,__io(p)); })
280 #define writeb_relaxed(v,c) __raw_writeb(v,c)

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