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Searched refs:__raw_writel (Results 1 – 25 of 177) sorted by relevance

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/arch/mips/alchemy/common/
A Dvss.c34 __raw_writel(0x01, base + VSS_FTR); in __enable_block()
36 __raw_writel(0x03, base + VSS_FTR); in __enable_block()
38 __raw_writel(0x07, base + VSS_FTR); in __enable_block()
40 __raw_writel(0x0f, base + VSS_FTR); in __enable_block()
43 __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */ in __enable_block()
46 __raw_writel(2, base + VSS_CLKRST); /* deassert reset */ in __enable_block()
49 __raw_writel(0x1f, base + VSS_FTR); /* enable isolation cells */ in __enable_block()
60 __raw_writel(0, base + VSS_GATE); /* disable FSM */ in __disable_block()
62 __raw_writel(3, base + VSS_CLKRST); /* assert reset */ in __disable_block()
64 __raw_writel(1, base + VSS_CLKRST); /* disable clock */ in __disable_block()
[all …]
A Dirq.c293 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic0_unmask()
523 __raw_writel(l, r + AU1300_GPIC_PINCFG); in au1300_gpic_chgcfg()
608 __raw_writel(bit, r + AU1300_GPIC_IDIS); in au1300_gpic_mask()
625 __raw_writel(bit, r + AU1300_GPIC_IEN); in au1300_gpic_unmask()
749 __raw_writel(d[0], base + IC_CFG0SET); in alchemy_ic_resume_one()
750 __raw_writel(d[1], base + IC_CFG1SET); in alchemy_ic_resume_one()
751 __raw_writel(d[2], base + IC_CFG2SET); in alchemy_ic_resume_one()
752 __raw_writel(d[3], base + IC_SRCSET); in alchemy_ic_resume_one()
753 __raw_writel(d[4], base + IC_ASSIGNSET); in alchemy_ic_resume_one()
754 __raw_writel(d[5], base + IC_WAKESET); in alchemy_ic_resume_one()
[all …]
A Dusb.c112 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
118 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
134 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ohci_control()
145 __raw_writel(0, base + USB_DWC_CTRL7); in __au1300_ohci_control()
156 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ohci_control()
170 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ehci_control()
175 __raw_writel(r, base + USB_DWC_CTRL1); in __au1300_ehci_control()
192 __raw_writel(r, base + USB_DWC_CTRL1); in __au1300_ehci_control()
417 __raw_writel(r, base); in au1000_usb_init()
519 __raw_writel(0, base + 0x04); in au1000_usb_pm()
[all …]
/arch/arm/mach-mmp/
A Dtime.c50 __raw_writel(1, mmp_timer_base + TMR_CVWR(1)); in timer_read()
70 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); in timer_interrupt()
75 __raw_writel(0x02, mmp_timer_base + TMR_CER); in timer_interrupt()
92 __raw_writel(0x02, mmp_timer_base + TMR_CER); in timer_set_next_event()
97 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); in timer_set_next_event()
98 __raw_writel(0x01, mmp_timer_base + TMR_IER(0)); in timer_set_next_event()
108 __raw_writel(0x03, mmp_timer_base + TMR_CER); in timer_set_next_event()
158 __raw_writel(ccr, mmp_timer_base + TMR_CCR); in timer_config()
161 __raw_writel(0x2, mmp_timer_base + TMR_CMR); in timer_config()
165 __raw_writel(0x0, mmp_timer_base + TMR_IER(0)); in timer_config()
[all …]
/arch/mips/sgi-ip22/
A Dip22-nvram.c36 __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \
37 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
38 __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \
40 __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \
41 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
45 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
46 __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \
47 __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \
48 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
69 __raw_writel(__raw_readl(ctrl) | EEPROM_ECLK, ctrl); in eeprom_cmd()
[all …]
/arch/mips/kernel/
A Dcevt-txx9.c63 __raw_writel(TCR_BASE, &tmrptr->tcr); in txx9_clocksource_init()
64 __raw_writel(0, &tmrptr->tisr); in txx9_clocksource_init()
85 __raw_writel(0, &tmrptr->tisr); in txx9tmr_stop_and_clear()
122 __raw_writel(0, &tmrptr->itmr); in txx9tmr_set_state_shutdown()
134 __raw_writel(0, &tmrptr->itmr); in txx9tmr_tick_resume()
147 __raw_writel(delta, &tmrptr->cpra); in txx9tmr_set_next_event()
186 __raw_writel(0, &tmrptr->itmr); in txx9_clockevent_init()
214 __raw_writel(0, &tmrptr->tisr); in txx9_tmr_init()
216 __raw_writel(0, &tmrptr->itmr); in txx9_tmr_init()
217 __raw_writel(0, &tmrptr->ccdr); in txx9_tmr_init()
[all …]
A Dirq_txx9.c72 __raw_writel((__raw_readl(ilrp) & ~(0xff << ofs)) in txx9_irq_unmask()
83 __raw_writel((__raw_readl(ilrp) & ~(0xff << ofs)) in txx9_irq_mask()
96 __raw_writel(TXx9_IRSCR_EIClrE | irq_nr, &txx9_ircptr->scr); in txx9_irq_mask_ack()
122 __raw_writel(cr, crp); in txx9_irq_set_type()
149 __raw_writel(0, &txx9_ircptr->imr); in txx9_irq_init()
151 __raw_writel(0, &txx9_ircptr->ilr[i]); in txx9_irq_init()
154 __raw_writel(0, &txx9_ircptr->cr[i]); in txx9_irq_init()
156 __raw_writel(TXx9_IRCER_ICE, &txx9_ircptr->cer); in txx9_irq_init()
157 __raw_writel(irc_elevel, &txx9_ircptr->imr); in txx9_irq_init()
/arch/arm/mach-pxa/
A Dsmemc.c37 __raw_writel(msc[0], MSC0); in pxa3xx_smemc_resume()
38 __raw_writel(msc[1], MSC1); in pxa3xx_smemc_resume()
39 __raw_writel(sxcnfg, SXCNFG); in pxa3xx_smemc_resume()
40 __raw_writel(memclkcfg, MEMCLKCFG); in pxa3xx_smemc_resume()
41 __raw_writel(csadrcfg[0], CSADRCFG0); in pxa3xx_smemc_resume()
42 __raw_writel(csadrcfg[1], CSADRCFG1); in pxa3xx_smemc_resume()
43 __raw_writel(csadrcfg[2], CSADRCFG2); in pxa3xx_smemc_resume()
44 __raw_writel(csadrcfg[3], CSADRCFG3); in pxa3xx_smemc_resume()
46 __raw_writel(0x2, CSMSADRCFG); in pxa3xx_smemc_resume()
65 __raw_writel(0x2, CSMSADRCFG); in smemc_init()
A Dgeneric.c62 __raw_writel(mcmem, MCMEM(sock)); in pxa_smemc_set_pcmcia_timing()
63 __raw_writel(mcatt, MCATT(sock)); in pxa_smemc_set_pcmcia_timing()
64 __raw_writel(mcio, MCIO(sock)); in pxa_smemc_set_pcmcia_timing()
72 __raw_writel(0, MECR); in pxa_smemc_set_pcmcia_socket()
79 __raw_writel(MECR_CIT, MECR); in pxa_smemc_set_pcmcia_socket()
83 __raw_writel(MECR_CIT | MECR_NOS, MECR); in pxa_smemc_set_pcmcia_socket()
A Dirq.c72 __raw_writel(icmr, base + ICMR); in pxa_mask_irq()
82 __raw_writel(icmr, base + ICMR); in pxa_unmask_irq()
129 __raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw)); in pxa_irq_map()
159 __raw_writel(0, base + ICMR); /* disable all IRQs */ in pxa_init_irq_common()
160 __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ in pxa_init_irq_common()
163 __raw_writel(1, irq_base(0) + ICCR); in pxa_init_irq_common()
189 __raw_writel(0, base + ICMR); in pxa_irq_suspend()
207 __raw_writel(saved_icmr[i], base + ICMR); in pxa_irq_resume()
208 __raw_writel(0, base + ICLR); in pxa_irq_resume()
213 __raw_writel(saved_ipr[i], pxa_irq_base + IPR(i)); in pxa_irq_resume()
[all …]
/arch/mips/loongson32/common/
A Dirq.c28 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_ack()
37 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask()
46 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask_ack()
48 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_mask_ack()
57 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_unmask()
68 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
74 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
80 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
86 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
92 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
[all …]
/arch/sh/mm/
A Dtlb-pteaex.c32 __raw_writel(vpn, MMU_PTEH); in __update_tlb()
35 __raw_writel(get_asid(), MMU_PTEAEX); in __update_tlb()
47 __raw_writel(pte.pte_high, MMU_PTEA); in __update_tlb()
56 __raw_writel(pteval, MMU_PTEL); in __update_tlb()
73 __raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
74 __raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
75 __raw_writel(page, MMU_ITLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
76 __raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
98 __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
101 __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
A Dtlb-sh4.c30 __raw_writel(vpn, MMU_PTEH); in __update_tlb()
42 __raw_writel(pte.pte_high, MMU_PTEA); in __update_tlb()
48 __raw_writel(copy_ptea_attributes(pteval), MMU_PTEA); in __update_tlb()
58 __raw_writel(pteval, MMU_PTEL); in __update_tlb()
78 __raw_writel(data, addr); in local_flush_tlb_one()
100 __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
103 __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
/arch/m68k/coldfire/
A Dpci.c71 __raw_writel(PCICAR_E | addr, PCICAR); in mcf_pci_readconfig()
87 __raw_writel(0, PCICAR); in mcf_pci_readconfig()
103 __raw_writel(PCICAR_E | addr, PCICAR); in mcf_pci_writeconfig()
115 __raw_writel(cpu_to_le32(value), addr); in mcf_pci_writeconfig()
119 __raw_writel(0, PCICAR); in mcf_pci_writeconfig()
178 __raw_writel(PCIGSCR_RESET, PCIGSCR); in mcf_pci_init()
179 __raw_writel(0, PCITCR); in mcf_pci_init()
195 __raw_writel(PCICR1_LT(32) | PCICR1_CL(8), PCICR1); in mcf_pci_init()
196 __raw_writel(0, PCICR2); in mcf_pci_init()
214 __raw_writel(CONFIG_RAMBASE, PCIBAR1); in mcf_pci_init()
[all …]
/arch/sh/drivers/pci/
A Dpci-sh7780.c127 __raw_writel(cmd, hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
140 __raw_writel(cmd, hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
169 __raw_writel(0, hose->reg_base + SH4_PCIAINT); in sh7780_pci_setup_irqs()
231 __raw_writel(tmp, hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
241 __raw_writel(tmp, hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
258 __raw_writel(PCIECR_ENBL, PCIECR); in sh7780_pci_init()
296 __raw_writel(SH4_PCICR_PREFIX | PCICR_ENDIANNESS, in sh7780_pci_init()
315 __raw_writel(0, chan->reg_base + SH4_PCILAR1); in sh7780_pci_init()
316 __raw_writel(0, chan->reg_base + SH4_PCILSR1); in sh7780_pci_init()
324 __raw_writel(((memsize - SZ_1M) & 0x1ff00000) | 1, in sh7780_pci_init()
[all …]
/arch/mips/pci/
A Dops-tx4927.c64 __raw_writel(((bus->number & 0xff) << 0x10) in mkaddr()
130 __raw_writel(val, &pcicptr->g2pcfgdata); in icd_writel()
265 __raw_writel(0, &pcicptr->g2pmmask[i]); in tx4927_pcic_setup()
270 __raw_writel((channel->mem_resource->end in tx4927_pcic_setup()
288 __raw_writel(0, &pcicptr->p2gm0plbase); in tx4927_pcic_setup()
289 __raw_writel(0, &pcicptr->p2gm0pubase); in tx4927_pcic_setup()
306 __raw_writel((tx4927_pci_opts.gbwc << 16) in tx4927_pcic_setup()
325 __raw_writel(0, &pcicptr->pcicfg1); in tx4927_pcic_setup()
350 __raw_writel(0, &pcicptr->pbabm); in tx4927_pcic_setup()
514 __raw_writel(0, &pcicptr->pbabm); in tx4927_quirk_slc90e66_bridge()
[all …]
/arch/sh/kernel/cpu/sh4a/
A Dubc.c34 __raw_writel(UBC_CBR_CE | info->len | info->type, UBC_CBR(idx)); in sh4a_ubc_enable()
35 __raw_writel(info->address, UBC_CAR(idx)); in sh4a_ubc_enable()
40 __raw_writel(0, UBC_CBR(idx)); in sh4a_ubc_disable()
41 __raw_writel(0, UBC_CAR(idx)); in sh4a_ubc_disable()
50 __raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE, in sh4a_ubc_enable_all()
59 __raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE, in sh4a_ubc_disable_all()
82 __raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR); in sh4a_ubc_clear_triggered_mask()
112 __raw_writel(0, UBC_CBCR); in sh4a_ubc_init()
115 __raw_writel(0, UBC_CAMR(i)); in sh4a_ubc_init()
116 __raw_writel(0, UBC_CBR(i)); in sh4a_ubc_init()
[all …]
A Dsmp-shx3.c36 __raw_writel(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */ in ipi_interrupt_handler()
51 __raw_writel(__raw_readl(STBCR_REG(cpu)) | STBCR_LTSLP, STBCR_REG(cpu)); in shx3_smp_setup()
87 __raw_writel(entry_point, RESET_REG(cpu)); in shx3_start_cpu()
89 __raw_writel(virt_to_phys(entry_point), RESET_REG(cpu)); in shx3_start_cpu()
92 __raw_writel(STBCR_MSTP, STBCR_REG(cpu)); in shx3_start_cpu()
98 __raw_writel(STBCR_RESET | STBCR_LTSLP, STBCR_REG(cpu)); in shx3_start_cpu()
112 __raw_writel(1 << (message << 2), addr); /* C0INTICI..CnINTICI */ in shx3_send_ipi()
117 __raw_writel(STBCR_MSTP, STBCR_REG(cpu)); in shx3_update_boot_vector()
120 __raw_writel(STBCR_RESET, STBCR_REG(cpu)); in shx3_update_boot_vector()
/arch/arm/mach-lpc32xx/
A Dserial.c110 __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg); in lpc32xx_serial_init()
117 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
118 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); in lpc32xx_serial_init()
123 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
127 __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE); in lpc32xx_serial_init()
131 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
132 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); in lpc32xx_serial_init()
136 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
142 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); in lpc32xx_serial_init()
147 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); in lpc32xx_serial_init()
/arch/mips/ath79/
A Dcommon.c61 __raw_writel(0x1, flush_reg); in ath79_ddr_wb_flush()
66 __raw_writel(0x1, flush_reg); in ath79_ddr_wb_flush()
76 __raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0x0); in ath79_ddr_set_pci_windows()
77 __raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 0x4); in ath79_ddr_set_pci_windows()
78 __raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 0x8); in ath79_ddr_set_pci_windows()
79 __raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 0xc); in ath79_ddr_set_pci_windows()
80 __raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 0x10); in ath79_ddr_set_pci_windows()
81 __raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 0x14); in ath79_ddr_set_pci_windows()
82 __raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 0x18); in ath79_ddr_set_pci_windows()
83 __raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 0x1c); in ath79_ddr_set_pci_windows()
/arch/sh/boards/mach-sh7763rdp/
A Dirq.c28 __raw_writel(1 << 25, INTC_INT2MSKCR); in init_sh7763rdp_IRQ()
31 __raw_writel((__raw_readl(INTC_INT2PRI7) & 0xFF00FFFF) | 0x000F0000, in init_sh7763rdp_IRQ()
35 __raw_writel(1 << 17, INTC_INT2MSKCR1); in init_sh7763rdp_IRQ()
38 __raw_writel(1 << 16, INTC_INT2MSKCR1); in init_sh7763rdp_IRQ()
41 __raw_writel(1 << 8, INTC_INT2MSKCR); in init_sh7763rdp_IRQ()
/arch/mips/include/asm/mach-au1x00/
A Dau1000_dma.h159 __raw_writel(DMA_BE0, chan->io + DMA_MODE_SET); in enable_dma_buffer0()
168 __raw_writel(DMA_BE1, chan->io + DMA_MODE_SET); in enable_dma_buffer1()
185 __raw_writel(DMA_GO, chan->io + DMA_MODE_SET); in start_dma()
197 __raw_writel(DMA_GO, chan->io + DMA_MODE_CLEAR); in halt_dma()
217 __raw_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR); in disable_dma()
247 __raw_writel(~mode, chan->io + DMA_MODE_CLEAR); in init_dma()
248 __raw_writel(mode, chan->io + DMA_MODE_SET); in init_dma()
318 __raw_writel(DMA_D0, chan->io + DMA_MODE_CLEAR); in clear_dma_done0()
327 __raw_writel(DMA_D1, chan->io + DMA_MODE_CLEAR); in clear_dma_done1()
346 __raw_writel(a, chan->io + DMA_BUFFER0_START); in set_dma_addr0()
[all …]
/arch/sh/kernel/cpu/sh3/
A Dprobe.c31 __raw_writel(data0&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr0); in cpu_probe()
33 __raw_writel(data1&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr1); in cpu_probe()
38 __raw_writel(data0, addr0); in cpu_probe()
41 __raw_writel(data2, addr1); in cpu_probe()
45 __raw_writel(data0&~SH_CACHE_VALID, addr0); in cpu_probe()
46 __raw_writel(data2&~SH_CACHE_VALID, addr1); in cpu_probe()
94 __raw_writel(CCR_CACHE_32KB, CCR3_REG); in cpu_probe()
96 __raw_writel(CCR_CACHE_16KB, CCR3_REG); in cpu_probe()
/arch/mips/include/asm/mach-rc32434/
A Ddma_v.h30 __raw_writel(0, &ch->dmac); in rc32434_halt_dma()
33 __raw_writel(0, &ch->dmas); in rc32434_halt_dma()
44 __raw_writel(0, &ch->dmandptr); in rc32434_start_dma()
45 __raw_writel(dma_addr, &ch->dmadptr); in rc32434_start_dma()
50 __raw_writel(dma_addr, &ch->dmandptr); in rc32434_chain_dma()
/arch/sh/boards/
A Dboard-magicpanelr2.c67 __raw_writel(0x36db0400, CS2BCR); in setup_chip_select()
69 __raw_writel(0x000003c0, CS2WCR); in setup_chip_select()
73 __raw_writel(0x00000200, CS4BCR); in setup_chip_select()
75 __raw_writel(0x00100981, CS4WCR); in setup_chip_select()
79 __raw_writel(0x00000200, CS5ABCR); in setup_chip_select()
81 __raw_writel(0x00100981, CS5AWCR); in setup_chip_select()
85 __raw_writel(0x00000200, CS5BBCR); in setup_chip_select()
87 __raw_writel(0x00100981, CS5BWCR); in setup_chip_select()
91 __raw_writel(0x00000200, CS6ABCR); in setup_chip_select()
93 __raw_writel(0x001009C1, CS6AWCR); in setup_chip_select()

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