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Searched refs:_flags (Results 1 – 19 of 19) sorted by relevance

/arch/arm64/include/asm/vdso/
A Dgetrandom.h19 static __always_inline ssize_t getrandom_syscall(void *_buffer, size_t _len, unsigned int _flags) in getrandom_syscall() argument
23 register unsigned int flags asm ("x2") = _flags; in getrandom_syscall()
/arch/loongarch/include/asm/vdso/
A Dgetrandom.h13 static __always_inline ssize_t getrandom_syscall(void *_buffer, size_t _len, unsigned int _flags) in getrandom_syscall() argument
19 register unsigned int flags asm("a2") = _flags; in getrandom_syscall()
/arch/riscv/include/asm/vdso/
A Dgetrandom.h12 static __always_inline ssize_t getrandom_syscall(void *_buffer, size_t _len, unsigned int _flags) in getrandom_syscall() argument
18 register unsigned int flags asm("a2") = _flags; in getrandom_syscall()
/arch/s390/include/asm/
A Dfpu.h232 int _flags = (flags); \
234 kernel_fpu_check_size(_flags, ARRAY_SIZE(s->vxrs)); \
235 _kernel_fpu_begin((struct kernel_fpu *)s, _flags); \
241 int _flags = (flags); \
243 kernel_fpu_check_size(_flags, ARRAY_SIZE(s->vxrs)); \
244 _kernel_fpu_end((struct kernel_fpu *)s, _flags); \
/arch/sh/kernel/cpu/sh4a/
A Dclock-sh7366.c108 #define DIV4(_reg, _bit, _mask, _flags) \ argument
109 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
128 #define MSTP(_parent, _reg, _bit, _flags) \ argument
129 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
A Dclock-sh7343.c105 #define DIV4(_reg, _bit, _mask, _flags) \ argument
106 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
125 #define MSTP(_parent, _reg, _bit, _flags) \ argument
126 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
A Dclock-sh7757.c62 #define DIV4(_bit, _mask, _flags) \ argument
63 SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)
A Dclock-shx3.c61 #define DIV4(_bit, _mask, _flags) \ argument
62 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
A Dclock-sh7785.c66 #define DIV4(_bit, _mask, _flags) \ argument
67 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
A Dclock-sh7786.c67 #define DIV4(_bit, _mask, _flags) \ argument
68 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
A Dclock-sh7722.c108 #define DIV4(_reg, _bit, _mask, _flags) \ argument
109 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
A Dclock-sh7734.c69 #define DIV4(_reg, _bit, _mask, _flags) \ argument
70 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
A Dclock-sh7723.c111 #define DIV4(_reg, _bit, _mask, _flags) \ argument
112 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
A Dclock-sh7724.c150 #define DIV4(_reg, _bit, _mask, _flags) \ argument
151 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
/arch/sh/kernel/cpu/sh2a/
A Dclock-sh7264.c77 #define DIV4(_reg, _bit, _mask, _flags) \ argument
78 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
A Dclock-sh7269.c105 #define DIV4(_reg, _bit, _mask, _flags) \ argument
106 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
/arch/arm/mach-omap2/
A Dclockdomain.c852 clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED; in clkdm_sleep_nolock()
906 clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED; in clkdm_wakeup_nolock()
970 clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED; in clkdm_allow_idle_nolock()
1025 clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED; in clkdm_deny_idle_nolock()
A Dclockdomain.h132 u8 _flags; member
/arch/sparc/kernel/
A Dperf_event.c1114 static void sparc_pmu_del(struct perf_event *event, int _flags) in sparc_pmu_del() argument

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