Searched refs:aff0 (Results 1 – 2 of 2) sorted by relevance
40 and \dst, \mpidr, #0xff @ mask=aff041 ARM( mov \dst, \dst, lsr \rs0 ) @ dst=aff0>>rs0
1099 u32 sgi, aff0; in vgic_v3_dispatch_sgi() local1123 for_each_set_bit(aff0, &target_cpus, hweight_long(ICC_SGI1R_TARGET_LIST_MASK)) { in vgic_v3_dispatch_sgi()1124 c_vcpu = kvm_mpidr_to_vcpu(kvm, mpidr | aff0); in vgic_v3_dispatch_sgi()
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