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/arch/arm64/boot/dts/freescale/
A Dimx8mp-nominal.dtsi7 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
19 assigned-clock-rates = <0>, <0>,
30 assigned-clock-rates = <800000000>;
42 assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>,
52 assigned-clock-rates = <400000000>;
56 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
64 assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,
70 assigned-clock-rates = <800000000>,
93 assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;
95 assigned-clock-rates = <600000000>;
[all …]
A Dimx8mm-overdrive.dtsi4 assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
6 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
7 assigned-clock-rates = <0>, <1000000000>;
11 assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
13 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
14 assigned-clock-rates = <0>, <1000000000>;
18 assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
22 assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
25 assigned-clock-rates = <750000000>,
A Dimx8-ss-dma.dtsi35 assigned-clock-rates = <60000000>;
53 assigned-clock-rates = <60000000>;
71 assigned-clock-rates = <60000000>;
89 assigned-clock-rates = <60000000>;
103 assigned-clock-rates = <80000000>;
117 assigned-clock-rates = <80000000>;
131 assigned-clock-rates = <80000000>;
145 assigned-clock-rates = <80000000>;
160 assigned-clock-rates = <24000000>;
321 assigned-clock-rates = <24000000>;
[all …]
A Dimx8mn-evk.dtsi310 assigned-clock-rates = <24000000>;
334 assigned-clocks = <&clk IMX8MN_CLK_PDM>;
336 assigned-clock-rates = <196608000>;
377 assigned-clocks = <&clk IMX8MN_CLK_SAI2>;
379 assigned-clock-rates = <24576000>;
386 assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
388 assigned-clock-rates = <24576000>;
402 assigned-clock-rates = <24576000>;
409 assigned-clocks = <&clk IMX8MN_CLK_UART1>;
454 assigned-clock-rates = <200000000>;
[all …]
A Dimx8mn-overdrive.dtsi4 assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>,
9 assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
13 assigned-clock-rates = <600000000>,
A Dimx8mq-mnt-reform2.dts105 assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
106 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
107 assigned-clock-rates = <25000000>;
175 assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
176 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
177 /delete-property/assigned-clock-rates;
235 assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
236 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
237 assigned-clock-rates = <25000000>;
274 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
[all …]
A Dimx8mm-phygate-tauri-l-rs232-rs232.dtso33 assigned-clocks = <&clk IMX8MM_CLK_UART2>;
34 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
42 assigned-clocks = <&clk IMX8MM_CLK_UART4>;
43 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
A Dimx8mp.dtsi768 assigned-clock-rates = <0>, <0>,
1046 assigned-clock-rates = <80000000>;
1063 assigned-clock-rates = <80000000>;
1080 assigned-clock-rates = <80000000>;
1133 assigned-clock-rates = <40000000>;
1148 assigned-clock-rates = <40000000>;
1325 assigned-clock-rates = <80000000>;
2170 assigned-clock-rates = <10000000>;
2211 assigned-clock-rates = <10000000>;
2268 assigned-clock-rates = <800000000>;
[all …]
A Dimx8mp-msc-sm2s-ep1.dts72 assigned-clocks = <&clk IMX8MP_CLK_CLKOUT1_SEL>;
73 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
74 assigned-clock-rates = <24000000>;
89 assigned-clocks = <&clk IMX8MP_CLK_SAI2>;
90 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
91 assigned-clock-rates = <12288000>;
A Dimx8-ss-lvds1.dtsi80 assigned-clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>;
81 assigned-clock-rates = <24000000>;
96 assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
97 assigned-clock-rates = <24000000>;
109 assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
110 assigned-clock-rates = <24000000>;
A Dimx8ulp.dtsi303 assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
370 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
372 assigned-clock-rates = <48000000>;
383 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
385 assigned-clock-rates = <48000000>;
416 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
418 assigned-clock-rates = <48000000>;
431 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
433 assigned-clock-rates = <48000000>;
476 assigned-clock-rates = <48000000>;
[all …]
/arch/arm/boot/dts/nxp/imx/
A Dimx7ulp.dtsi154 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
156 assigned-clock-rates = <24000000>;
166 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
168 assigned-clock-rates = <48000000>;
175 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
263 assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
287 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
338 assigned-clock-rates = <48000000>;
351 assigned-clock-rates = <48000000>;
363 assigned-clock-rates = <48000000>;
[all …]
A Dimx7d-cl-som-imx7.dts47 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
49 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
50 assigned-clock-rates = <0>, <100000000>;
75 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
77 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
78 assigned-clock-rates = <0>, <100000000>;
197 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
198 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
212 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
213 assigned-clock-rates = <400000000>;
A Dimx7d-pico.dtsi105 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
107 assigned-clock-parents = <&clks IMX7D_CKIL>;
108 assigned-clock-rates = <0>, <32768>;
132 assigned-clock-rates = <0>, <100000000>;
286 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
289 assigned-clock-rates = <0>, <24576000>;
321 assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
329 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
338 assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
387 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
[all …]
/arch/arm64/boot/dts/xilinx/
A Dzynqmp-clk-ccf.dtsi170 assigned-clocks = <&zynqmp_clk GEM_TSU>;
177 assigned-clocks = <&zynqmp_clk GEM_TSU>;
184 assigned-clocks = <&zynqmp_clk GEM_TSU>;
191 assigned-clocks = <&zynqmp_clk GEM_TSU>;
220 assigned-clocks = <&zynqmp_clk SDIO0_REF>;
225 assigned-clocks = <&zynqmp_clk SDIO1_REF>;
254 assigned-clocks = <&zynqmp_clk UART0_REF>;
259 assigned-clocks = <&zynqmp_clk UART1_REF>;
264 assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
294 assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */
[all …]
/arch/arm64/boot/dts/rockchip/
A Drk3568-fastrhino-r68s.dts30 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
31 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
32 assigned-clock-rates = <0>, <125000000>;
46 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
47 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
48 assigned-clock-rates = <0>, <125000000>;
/arch/arm/boot/dts/samsung/
A Dexynos4412-odroid-common.dtsi129 assigned-clocks = <&clock CLK_FOUT_EPLL>;
130 assigned-clock-rates = <45158401>;
143 assigned-clock-rates = <0>, <0>,
211 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
214 assigned-clock-rates = <0>, <176000000>;
219 assigned-clocks = <&clock CLK_MOUT_FIMC1>,
222 assigned-clock-rates = <0>, <176000000>;
227 assigned-clocks = <&clock CLK_MOUT_FIMC2>,
230 assigned-clock-rates = <0>, <176000000>;
235 assigned-clocks = <&clock CLK_MOUT_FIMC3>,
[all …]
/arch/arm64/boot/dts/ti/
A Dk3-j784s4-j742s2-main-common.dtsi125 assigned-clocks = <&k3_clks 157 34>;
290 assigned-clocks = <&k3_clks 97 2>;
302 assigned-clocks = <&k3_clks 98 2>;
314 assigned-clocks = <&k3_clks 99 2>;
326 assigned-clocks = <&k3_clks 100 2>;
338 assigned-clocks = <&k3_clks 101 2>;
350 assigned-clocks = <&k3_clks 102 2>;
362 assigned-clocks = <&k3_clks 103 2>;
374 assigned-clocks = <&k3_clks 104 2>;
386 assigned-clocks = <&k3_clks 105 2>;
[all …]
A Dk3-j721s2-mcu-wakeup.dtsi173 assigned-clocks = <&k3_clks 35 1>;
188 assigned-clocks = <&k3_clks 83 1>;
202 assigned-clocks = <&k3_clks 84 1>;
216 assigned-clocks = <&k3_clks 85 1>;
230 assigned-clocks = <&k3_clks 86 1>;
244 assigned-clocks = <&k3_clks 87 1>;
258 assigned-clocks = <&k3_clks 88 1>;
272 assigned-clocks = <&k3_clks 89 1>;
286 assigned-clocks = <&k3_clks 90 1>;
300 assigned-clocks = <&k3_clks 91 1>;
[all …]
A Dk3-j784s4-j742s2-mcu-wakeup-common.dtsi172 assigned-clocks = <&k3_clks 35 2>;
187 assigned-clocks = <&k3_clks 117 2>;
201 assigned-clocks = <&k3_clks 118 2>;
215 assigned-clocks = <&k3_clks 119 2>;
229 assigned-clocks = <&k3_clks 120 2>;
243 assigned-clocks = <&k3_clks 121 2>;
257 assigned-clocks = <&k3_clks 122 2>;
271 assigned-clocks = <&k3_clks 123 2>;
285 assigned-clocks = <&k3_clks 124 2>;
645 assigned-clocks = <&k3_clks 0 2>;
[all …]
A Dk3-am654-pcie-usb2.dtso16 assigned-clocks = <&k3_clks 153 4>,
19 assigned-clock-parents = <&k3_clks 153 8>,
26 assigned-clocks = <&serdes1 AM654_SERDES_CMU_REFCLK>;
27 assigned-clock-parents = <&serdes0 AM654_SERDES_RO_REFCLK>;
A Dk3-j721s2-main.dtsi229 assigned-clocks = <&k3_clks 63 1>;
241 assigned-clocks = <&k3_clks 64 1>;
253 assigned-clocks = <&k3_clks 65 1>;
265 assigned-clocks = <&k3_clks 66 1>;
277 assigned-clocks = <&k3_clks 67 1>;
289 assigned-clocks = <&k3_clks 68 1>;
301 assigned-clocks = <&k3_clks 69 1>;
313 assigned-clocks = <&k3_clks 70 1>;
325 assigned-clocks = <&k3_clks 71 1>;
337 assigned-clocks = <&k3_clks 72 1>;
[all …]
A Dk3-am62-main.dtsi66 assigned-clocks = <&k3_clks 157 0>;
75 assigned-clocks = <&k3_clks 157 10>;
254 assigned-clocks = <&k3_clks 36 2>;
266 assigned-clocks = <&k3_clks 37 2>;
278 assigned-clocks = <&k3_clks 38 2>;
290 assigned-clocks = <&k3_clks 39 2>;
302 assigned-clocks = <&k3_clks 40 2>;
314 assigned-clocks = <&k3_clks 41 2>;
326 assigned-clocks = <&k3_clks 42 2>;
338 assigned-clocks = <&k3_clks 43 2>;
[all …]
/arch/riscv/boot/dts/starfive/
A Djh7110-starfive-visionfive-2-v1.3b.dts17 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
18 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
23 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
24 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
/arch/mips/boot/dts/img/
A Dpistachio.dtsi53 assigned-clock-rates = <100000000>, <33333334>;
71 assigned-clock-rates = <100000000>, <33333334>;
141 assigned-clocks = <&clk_core CLK_I2S_DIV>;
142 assigned-clock-rates = <12288000>;
162 assigned-clock-rates = <12288000>;
178 assigned-clocks = <&clk_core CLK_SPDIF_DIV>;
179 assigned-clock-rates = <12288000>;
752 assigned-clock-rates = <4000000>, <32768>;
763 assigned-clock-rates = <4000000>, <32768>;
789 assigned-clock-rates = <0>, <50000000>;
[all …]

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