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/arch/xtensa/include/asm/
A Dcacheasm.h51 __endla \ar, \at, _reps << (\line_width)
66 extui \at, \ar, 0, \line_width
67 add \as, \as, \at
69 __loops \ar, \as, \at, \line_width
71 __endla \ar, \at, (1 << (\line_width))
83 .macro ___unlock_dcache_all ar at
93 .macro ___unlock_icache_all ar at
113 .macro ___flush_dcache_all ar at
123 .macro ___invalidate_dcache_all ar at
133 .macro ___invalidate_icache_all ar at
[all …]
A Dasmmacro.h54 loop \at, 99f
72 extui \at, \at, \incr_log2, \mask_log2
74 srli \at, \at, \incr_log2
77 loop\cond \at, 99f
87 b\ncond \at, 99f
91 slli \at, \at, \incr_log2
92 add \at, \ar, \at
108 sub \at, \as, \ar
110 addi \at, \at, (1 << \incr_log2) - 1
111 srli \at, \at, \incr_log2
[all …]
A Dasm-uaccess.h49 .macro user_ok aa, as, at, error
50 movi \at, __XTENSA_UL_CONST(TASK_SIZE)
51 bgeu \as, \at, \error
52 sub \at, \at, \as
53 bgeu \aa, \at, \error
79 .macro access_ok aa, as, at, sp, error
80 user_ok \aa, \as, \at, \error
/arch/xtensa/lib/
A Dmulsi3.S6 .macro do_addx2 dst, as, at, tmp
8 addx2 \dst, \as, \at
11 add \dst, \tmp, \at
15 .macro do_addx4 dst, as, at, tmp
17 addx4 \dst, \as, \at
20 add \dst, \tmp, \at
24 .macro do_addx8 dst, as, at, tmp
26 addx8 \dst, \as, \at
29 add \dst, \tmp, \at
A Dumulsidi3.S163 .macro do_addx2 dst, as, at, tmp
165 addx2 \dst, \as, \at
168 add \dst, \tmp, \at
172 .macro do_addx4 dst, as, at, tmp
174 addx4 \dst, \as, \at
177 add \dst, \tmp, \at
181 .macro do_addx8 dst, as, at, tmp
183 addx8 \dst, \as, \at
186 add \dst, \tmp, \at
/arch/mips/math-emu/
A Dsp_mul.c24 unsigned int at; in ieee754sp_mul() local
127 at = lrm + (t << 16); in ieee754sp_mul()
128 hrm += at < lrm; in ieee754sp_mul()
129 lrm = at; in ieee754sp_mul()
133 at = lrm + (t << 16); in ieee754sp_mul()
134 hrm += at < lrm; in ieee754sp_mul()
135 lrm = at; in ieee754sp_mul()
A Ddp_mul.c24 u64 at; in ieee754dp_mul() local
129 at = lrm + (t << 32); in ieee754dp_mul()
130 hrm += at < lrm; in ieee754dp_mul()
131 lrm = at; in ieee754dp_mul()
137 at = lrm + (t << 32); in ieee754dp_mul()
138 hrm += at < lrm; in ieee754dp_mul()
139 lrm = at; in ieee754dp_mul()
A Ddp_maddf.c54 u64 at; in _dp_maddf() local
204 at = lrm + (t << 32); in _dp_maddf()
205 hrm += at < lrm; in _dp_maddf()
206 lrm = at; in _dp_maddf()
212 at = lrm + (t << 32); in _dp_maddf()
213 hrm += at < lrm; in _dp_maddf()
214 lrm = at; in _dp_maddf()
/arch/x86/events/intel/
A Dds.c915 for (at = base; at < top; at++) { in intel_pmu_drain_bts_buffer()
922 (kernel_ip(at->from) || kernel_ip(at->to))) in intel_pmu_drain_bts_buffer()
939 for (at = base; at < top; at++) { in intel_pmu_drain_bts_buffer()
942 (kernel_ip(at->from) || kernel_ip(at->to))) in intel_pmu_drain_bts_buffer()
2226 void *at; in get_next_pebs_record_by_bit() local
2239 for (at = base; at < top; at += cpuc->pebs_record_size) { in get_next_pebs_record_by_bit()
2245 return at; in get_next_pebs_record_by_bit()
2423 at = get_next_pebs_record_by_bit(at, top, bit); in __intel_pmu_pebs_events()
2520 for (at = base; at < top; at += x86_pmu.pebs_record_size) { in intel_pmu_drain_pebs_nhm()
2638 for (at = base; at < top; at += basic->format_size) { in intel_pmu_drain_pebs_icl()
[all …]
/arch/arm/boot/dts/st/
A Dstih418-b2264.dts25 /* u-boot puts hpen in SBC dmem at 0xb8 offset */
30 /* u-boot puts hpen in SBC dmem at 0xb8 offset */
35 /* u-boot puts hpen in SBC dmem at 0xb8 offset */
40 /* u-boot puts hpen in SBC dmem at 0xb8 offset */
/arch/mips/jazz/
A DKconfig9 the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
20 the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
30 the MIPS architecture, check out the Linux/MIPS FAQ on the WWW at
/arch/arm/mach-sti/
A DKconfig34 Electronics family StiH415 parts, primarily targeted at set-top-box
43 Electronics family StiH416 parts, primarily targeted at set-top-box
53 Electronics family StiH407 parts, targetted at set-top-box
/arch/arm/boot/dts/microchip/
A Daks-cdu.dts32 linux,rs485-enabled-at-boot-time;
38 linux,rs485-enabled-at-boot-time;
44 linux,rs485-enabled-at-boot-time;
/arch/arm/include/debug/
A Dvexpress.S27 @ should use UART at 0x10009000
29 @ at 0x1c090000
/arch/arm/mach-qcom/
A DKconfig19 bool "Reserve SMEM at the beginning of RAM"
21 Reserve 2MB at the beginning of the System RAM for shared mem.
/arch/m68k/hp300/
A DREADME.hp3004 The Linux/HP web page is at <http://www.tazenda.demon.co.uk/phil/linux-hp/>
9 The serial console is probably broken at the moment but the Topcat/HIL keyboard
/arch/arm/nwfpe/
A Dsoftfloat-macros9 International Computer Science Institute, located at Suite 600, 1947 Center
13 processor in collaboration with the University of California at Berkeley,
88 _plus_ the number of bits given in `count'. The shifted result is at most
98 integer part of the result is returned at the location pointed to by
100 described above, and is returned at the location pointed to by `z1Ptr'.)
138 which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
304 64-bit pieces which are stored at the locations pointed to by `z0Ptr',
341 are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
361 64-bit pieces which are stored at the locations pointed to by `z0Ptr',
456 into two 64-bit pieces which are stored at the locations pointed to by
[all …]
/arch/arm/boot/dts/ti/omap/
A Domap54xx-clocks.dtsi139 ti,index-starts-at-one;
187 ti,index-starts-at-one;
221 ti,index-starts-at-one;
249 ti,index-starts-at-one;
259 ti,index-starts-at-one;
269 ti,index-starts-at-one;
279 ti,index-starts-at-one;
289 ti,index-starts-at-one;
299 ti,index-starts-at-one;
309 ti,index-starts-at-one;
[all …]
/arch/arm/boot/dts/intel/ixp/
A Dintel-ixp46x-ixdp465.dts26 /* 32 MB of Flash mapped in at CS0 and CS1 */
31 /* Eraseblock at 0x1fe0000 */
/arch/arm64/boot/dts/renesas/
A Drzg2l-smarc.dtsi171 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
172 * SW2 should be at position 2->3 so that SER0_TX line is activated
173 * SW3 should be at position 2->3 so that SER0_RX line is activated
174 * SW4 should be at position 2->3 so that SER0_RTS# line is activated
A Drzg2lc-smarc.dtsi180 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
181 * SW2 should be at position 2->3 so that SER0_TX line is activated
182 * SW3 should be at position 2->3 so that SER0_RX line is activated
183 * SW4 should be at position 2->3 so that SER0_RTS# line is activated
/arch/parisc/
A DKconfig.debug9 to catch memory overwrites at runtime. For more advanced
21 updated consistently on SMP machines at the expense of some
/arch/xtensa/
A DKconfig.debug25 bool "Perform S32C1I instruction self-test at boot"
28 Enable this option to test S32C1I instruction behavior at boot.
46 exception (starting at address aligned on 16 byte boundary).
/arch/m68k/apollo/
A Dconfig.c148 unsigned char *at = (unsigned char *)apollo_timer; in dn_timer_int() local
153 READ_ONCE(*(at + 3)); in dn_timer_int()
154 READ_ONCE(*(at + 5)); in dn_timer_int()
/arch/x86/boot/
A Dsetup.ld48 ASSERT(setup_sects >= 5, "The setup must be at least 5 sectors in size");
49 ASSERT(setup_sects <= 64, "The setup must be at most 64 sectors in size");

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